Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets: remove sdram_controller_type parameter (minicon removed)

This commit is contained in:
Florent Kermarrec 2016-04-29 17:51:16 +02:00
parent 8c7332e75e
commit 3d71ba6e66
4 changed files with 11 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
litex/boards/targets/de0nano.py
View File

@ -98,8 +98,9 @@ class BaseSoC(SoCSDRAM):
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),)
sdram_module = IS42S16160(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC port to the Altera DE0 Nano")

4
litex/boards/targets/kc705.py
View File

@ -84,7 +84,7 @@ class BaseSoC(SoCSDRAM):
}
csr_map.update(SoCSDRAM.csr_map)
def __init__(self, toolchain="ise", sdram_controller_type="minicon", **kwargs):
def __init__(self, toolchain="ise", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
@ -95,7 +95,7 @@ class BaseSoC(SoCSDRAM):
if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.timing_settings)
if not self.integrated_rom_size:

5
litex/boards/targets/minispartan6.py
View File

@ -78,8 +78,9 @@ class BaseSoC(SoCSDRAM):
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = AS4C16M16(clk_freq, "1:1")
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def main():

5
litex/boards/targets/sim.py
View File

@ -46,8 +46,9 @@ class BaseSoC(SoCSDRAM):
write_latency=0
)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
self.register_sdram(self.sdrphy, "minicon",
sdram_module.geom_settings, sdram_module.timing_settings)
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# reduce memtest size to speed up simulation
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)