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use new Record.connect omit parameter (replace leave_out)

This commit is contained in:
Florent Kermarrec 2016-04-21 09:39:21 +02:00
parent c330e7be49
commit 3d98be0997
2 changed files with 6 additions and 6 deletions
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10
litex/soc/cores/sdram/phy/s6ddrphy.py
View File

@ -451,14 +451,14 @@ class S6QuarterRateDDRPHY(Module):
# DFI adaptation
# Commands and writes
dfi_leave_out = set(["rddata", "rddata_valid", "wrdata_en"])
dfi_omit = set(["rddata", "rddata_valid", "wrdata_en"])
self.comb += [
If(~phase_sel,
self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
).Else(
self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
),
]
wr_data_en = self.dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel

2
litex/soc/interconnect/stream.py
View File

@ -276,7 +276,7 @@ class Converter(Module):
else:
self.source = Endpoint([("data", nbits_to)])
self.comb += converter.source.connect(self.source,
leave_out=set(["valid_token_count"]))
omit=set(["valid_token_count"]))
class StrideConverter(Module):