Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

update to work with mac

This commit is contained in:
Yehowshua Immanuel 2020-02-14 17:53:25 -05:00
parent 18a9d4ff2f
commit 3da204edd6
8 changed files with 67 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
CONTRIBUTORS
View File

@ -70,3 +70,4 @@ Copyright (c) 2015-2019 William D. Jones <thor0505@comcast.net>
Copyright (c) 2013-2014 Yann Sionneau <yann.sionneau@gmail.com>
Copyright (c) 2015 Yves Delley <hack@delley.net>
Copyright (c) 2015 Zach Smith <IAmSparticle@gmail.com>
Copyright (c) 2020 Yehowshua Immanuel <yimmanuel3@gatech.edu>

38
README.md
View File

@ -1,4 +1,4 @@
![LiteX](https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png)
![LiteX](doc/litex.png)
```
Copyright 2012-2020 / EnjoyDigital
```
@ -95,6 +95,9 @@ Migen documentation can be found here: https://m-labs.hk/migen/manual
# Quick start guide (for advanced users)
0. Install Python 3.5+ and FPGA vendor's development tools.
1. Install Migen/LiteX and the LiteX's cores:
On MacOS, make sure you have [HomeBrew](https://brew.sh) installed. Then do, ``brew install wget``.
```sh
$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$ chmod +x litex_setup.py
@ -105,28 +108,47 @@ $ ./litex_setup.py init install --user (--user to install to user directory)
$ ./litex_setup.py update
```
3. Install a RISC-V toolchain:
For Linux:
```sh
$ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
$ tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
$ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
```
MacOS:
```sh
$ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin.tar.gz
$ tar -xvf riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin.tar.gz
$ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin/bin/
```
4. Build the target of your board...:
Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
5. ... and/or install Verilator and test LiteX on your computer:
Download and install Verilator: http://www.veripool.org/
On Fedora:
5. ... and/or install [Verilator](http://www.veripool.org/) and test LiteX on your computer
On Fedora:
```sh
$ sudo dnf install libevent-devel json-c-devel
```
On Ubuntu:
On Ubuntu:
```sh
$ sudo apt install libevent-dev libjson-c-dev
$ sudo apt install libevent-dev libjson-c-dev verilator
$ litex_sim
```
On MacOS:
```sh
$ brew install json-c verilator libevent
$ brew cask install tuntap
$ litex_sim
```
6. Run a terminal program on the board's serial port at 115200 8-N-1.
You should get the BIOS prompt.
You should get the BIOS prompt like the one below.
![bios_screenshot](doc/bios_screenshot.png)
# Contact
E-mail: florent@enjoy-digital.fr
E-mail: florent@enjoy-digital.fr

BIN
doc/bios_screenshot.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 45 KiB

14
litex/build/sim/core/Makefile
View File

@ -1,8 +1,16 @@
include variables.mak
UNAME_S := $(shell uname -s)
ifeq ($(UNAME_S),Darwin)
CFLAGS += -I/usr/local/include/
LDFLAGS += -L/usr/local/lib
LDFLAGS += -lpthread -ljson-c -lm -lstdc++ -ldl -levent
else
CC ?= gcc
CFLAGS += -Wall -$(OPT_LEVEL) -ggdb $(if $(COVERAGE), -DVM_COVERAGE)
LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent
endif
CC ?= gcc
CFLAGS += -Wall -$(OPT_LEVEL) -ggdb $(if $(COVERAGE), -DVM_COVERAGE)
LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent
CC_SRCS ?= "--cc dut.v"

5
litex/build/sim/core/modules/ethernet/Makefile
View File

@ -1,5 +1,6 @@
include ../variables.mak
CFLAGS += -Itapcfg/src/include
UNAME_S := $(shell uname -s)
all: $(OBJ_DIR)/ethernet.so
@ -8,7 +9,11 @@ include ../rules.mak
OBJS = $(addprefix $(OBJ_DIR)/, ethernet.o tapcfg.o taplog.o)
$(OBJ_DIR)/ethernet.so: $(OBJS)
ifeq ($(UNAME_S),Darwin)
$(CC) $(LDFLAGS) -o $@ $^
else
$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^
endif
$(OBJ_DIR)/tapcfg.o: tapcfg/src/lib/tapcfg.c
$(CC) $(CFLAGS) -c -o $@ $<

6
litex/build/sim/core/modules/rules.mak
View File

@ -1,8 +1,14 @@
UNAME_S := $(shell uname -s)
$(OBJ_DIR)/%.o: %.c
$(CC) -c $(CFLAGS) -I../.. -o $@ $<
$(OBJ_DIR)/%.so: $(OBJ_DIR)/%.o
ifeq ($(UNAME_S),Darwin)
$(CC) $(LDFLAGS) -o $@ $^
else
$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $<
endif
.PHONY: clean
clean:

10
litex/build/sim/core/modules/variables.mak
View File

@ -1,5 +1,13 @@
CC ?= gcc
CFLAGS += -Wall -O3 -ggdb -fPIC -Werror
UNAME_S := $(shell uname -s)
ifeq ($(UNAME_S),Darwin)
CFLAGS += -I/usr/local/include/
LDFLAGS += -L/usr/local/lib -ljson-c
CFLAGS += -Wall -O3 -ggdb -fPIC
else
CFLAGS += -Wall -O3 -ggdb -fPIC -Werror
endif
LDFLAGS += -levent -shared -fPIC
OBJ_DIR ?= .

5
litex/build/sim/core/modules/xgmii_ethernet/Makefile
View File

@ -1,5 +1,6 @@
include ../variables.mak
CFLAGS += -Itapcfg/src/include
UNAME_S := $(shell uname -s)
all: $(OBJ_DIR)/xgmii_ethernet.so
@ -8,7 +9,11 @@ include ../rules.mak
OBJS = $(addprefix $(OBJ_DIR)/, xgmii_ethernet.o tapcfg.o taplog.o)
$(OBJ_DIR)/xgmii_ethernet.so: $(OBJS)
ifeq ($(UNAME_S),Darwin)
$(CC) $(LDFLAGS) -o $@ $^
else
$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^
endif
$(OBJ_DIR)/tapcfg.o: tapcfg/src/lib/tapcfg.c
$(CC) $(CFLAGS) -c -o $@ $<