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vexiiriscv: Now use pll.locked for debug reset

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This commit is contained in:
Dolu1990 2024-09-03 07:58:24 +02:00
parent 19b3f24d9f
commit 3de5832b9c
1 changed files with 3 additions and 3 deletions
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6
litex/soc/cores/cpu/vexiiriscv/core.py
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@ -514,10 +514,10 @@ class VexiiRiscv(CPU):
if soc.get_build_name() == "sim":
self.comb += If(debug_ndmreset_rise, soc.crg.cd_sys.rst.eq(1))
else:
if hasattr(soc.crg, "rst"):
if hasattr(soc.crg.pll, "locked"):
self.comb += If(debug_ndmreset, soc.crg.pll.locked.eq(0))
elif hasattr(soc.crg, "rst"):
self.comb += If(debug_ndmreset_rise, soc.crg.rst.eq(1))
elif hasattr(soc.crg.pll, "reset"):
self.comb += If(debug_ndmreset_rise, soc.crg.pll.reset.eq(1))
else:
raise Exception("Pll has no reset ?")