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build/sim/litex_sim: Only compiles video module when used. 

Avoid additional SDL2 dependency for regular simulations.
This commit is contained in:
Florent Kermarrec 2023-02-10 19:08:13 +01:00
parent 1f08fe3286
commit 3de5f20496
4 changed files with 24 additions and 11 deletions
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4
litex/build/sim/core/Makefile
View File

@ -10,11 +10,11 @@ ifeq ($(UNAME_S),Darwin)
CFLAGS += -I/opt/homebrew/include
LDFLAGS += -L/opt/homebrew/lib
endif
LDFLAGS += -lpthread -ljson-c -lz -lm -lstdc++ -ldl -levent
LDFLAGS += -lpthread -ljson-c -lz -lm -lstdc++ -ldl -levent $(if $(VIDEO), -lSDL2)
else
CC ?= gcc
CFLAGS += -ggdb
LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -lSDL2
LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent $(if $(VIDEO), -lSDL2)
endif
CFLAGS += -Wall -$(OPT_LEVEL) $(if $(COVERAGE), -DVM_COVERAGE) $(if $(TRACE_FST), -DTRACE_FST)

2
litex/build/sim/core/modules/Makefile
View File

@ -1,5 +1,5 @@
include ../variables.mak
MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker spdeeprom gmii_ethernet video
MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker spdeeprom gmii_ethernet $(if $(VIDEO), video)
.PHONY: $(MODULES) $(EXTRA_MOD_LIST)
all: $(MODULES) $(EXTRA_MOD_LIST)

24
litex/build/sim/verilator.py
View File

@ -106,7 +106,7 @@ extern "C" void litex_sim_init(void **out)
tools.write_to_file("sim_init.cpp", content)
def _generate_sim_variables(include_paths, extra_mods, extra_mods_path):
def _generate_sim_variables(include_paths, extra_mods, extra_mods_path, video):
tapcfg_dir = get_data_mod("misc", "tapcfg").data_location
include = ""
for path in include_paths:
@ -115,7 +115,8 @@ def _generate_sim_variables(include_paths, extra_mods, extra_mods_path):
SRC_DIR = {}
INC_DIR = {}
TAPCFG_DIRECTORY = {}
""".format(core_directory, include, tapcfg_dir)
VIDEO = {}
""".format(core_directory, include, tapcfg_dir, int(video))
if extra_mods:
modlist = " ".join(extra_mods)
@ -123,6 +124,7 @@ TAPCFG_DIRECTORY = {}
content += "EXTRA_MOD_BASE_DIR = " + extra_mods_path + "\n"
tools.write_to_file(extra_mods_path + "/variables.mak", content)
tools.write_to_file("variables.mak", content)
@ -131,7 +133,7 @@ def _generate_sim_config(config):
tools.write_to_file("sim_config.js", content)
def _build_sim(build_name, sources, jobs, threads, coverage, opt_level="O3", trace_fst=False):
def _build_sim(build_name, sources, jobs, threads, coverage, opt_level="O3", trace_fst=False, video=False):
makefile = os.path.join(core_directory, 'Makefile')
cc_srcs = []
@ -149,6 +151,7 @@ make -C . -f {} {} {} {} {} {} {}
"COVERAGE=1" if coverage else "",
"OPT_LEVEL={}".format(opt_level),
"TRACE_FST=1" if trace_fst else "",
"VIDEO=1" if video else "",
)
build_script_file = "build_" + build_name + ".sh"
tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
@ -200,6 +203,7 @@ class SimVerilatorToolchain:
sim_config = None,
coverage = False,
opt_level = "O0",
video = False,
trace = False,
trace_fst = False,
trace_start = 0,
@ -237,14 +241,24 @@ class SimVerilatorToolchain:
_generate_sim_variables(platform.verilog_include_paths,
extra_mods,
extra_mods_path)
extra_mods_path,
video)
# Generate sim config
if sim_config:
_generate_sim_config(sim_config)
# Build
_build_sim(build_name, platform.sources, jobs, threads, coverage, opt_level, trace_fst)
_build_sim(
build_name = build_name,
sources = platform.sources,
jobs = jobs,
threads = threads,
coverage = coverage,
opt_level = opt_level,
trace_fst = trace_fst,
video = video,
)
# Run
if run:

3
litex/tools/litex_sim.py
View File

@ -574,11 +574,10 @@ def main():
generate_gtkw_savefile(builder, vns, args.trace_fst)
builder = Builder(soc, **parser.builder_argdict)
print(parser.builder_argdict)
builder.build(
sim_config = sim_config,
interactive = not args.non_interactive,
video = args.with_video_framebuffer or args.with_video_terminal,
pre_run_callback = pre_run_callback,
**parser.toolchain_argdict,
)