build/sim/litex_sim: Only compiles video module when used.
Avoid additional SDL2 dependency for regular simulations.
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parent
1f08fe3286
commit
3de5f20496
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@ -10,11 +10,11 @@ ifeq ($(UNAME_S),Darwin)
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CFLAGS += -I/opt/homebrew/include
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LDFLAGS += -L/opt/homebrew/lib
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endif
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LDFLAGS += -lpthread -ljson-c -lz -lm -lstdc++ -ldl -levent
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LDFLAGS += -lpthread -ljson-c -lz -lm -lstdc++ -ldl -levent $(if $(VIDEO), -lSDL2)
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else
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CC ?= gcc
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CFLAGS += -ggdb
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LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent -lSDL2
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LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent $(if $(VIDEO), -lSDL2)
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endif
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CFLAGS += -Wall -$(OPT_LEVEL) $(if $(COVERAGE), -DVM_COVERAGE) $(if $(TRACE_FST), -DTRACE_FST)
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@ -1,5 +1,5 @@
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include ../variables.mak
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MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker spdeeprom gmii_ethernet video
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MODULES = xgmii_ethernet ethernet serial2console serial2tcp clocker spdeeprom gmii_ethernet $(if $(VIDEO), video)
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.PHONY: $(MODULES) $(EXTRA_MOD_LIST)
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all: $(MODULES) $(EXTRA_MOD_LIST)
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@ -106,7 +106,7 @@ extern "C" void litex_sim_init(void **out)
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tools.write_to_file("sim_init.cpp", content)
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def _generate_sim_variables(include_paths, extra_mods, extra_mods_path):
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def _generate_sim_variables(include_paths, extra_mods, extra_mods_path, video):
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tapcfg_dir = get_data_mod("misc", "tapcfg").data_location
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include = ""
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for path in include_paths:
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@ -115,7 +115,8 @@ def _generate_sim_variables(include_paths, extra_mods, extra_mods_path):
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SRC_DIR = {}
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INC_DIR = {}
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TAPCFG_DIRECTORY = {}
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""".format(core_directory, include, tapcfg_dir)
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VIDEO = {}
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""".format(core_directory, include, tapcfg_dir, int(video))
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if extra_mods:
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modlist = " ".join(extra_mods)
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@ -123,6 +124,7 @@ TAPCFG_DIRECTORY = {}
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content += "EXTRA_MOD_BASE_DIR = " + extra_mods_path + "\n"
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tools.write_to_file(extra_mods_path + "/variables.mak", content)
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tools.write_to_file("variables.mak", content)
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@ -131,7 +133,7 @@ def _generate_sim_config(config):
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tools.write_to_file("sim_config.js", content)
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def _build_sim(build_name, sources, jobs, threads, coverage, opt_level="O3", trace_fst=False):
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def _build_sim(build_name, sources, jobs, threads, coverage, opt_level="O3", trace_fst=False, video=False):
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makefile = os.path.join(core_directory, 'Makefile')
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cc_srcs = []
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@ -149,6 +151,7 @@ make -C . -f {} {} {} {} {} {} {}
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"COVERAGE=1" if coverage else "",
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"OPT_LEVEL={}".format(opt_level),
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"TRACE_FST=1" if trace_fst else "",
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"VIDEO=1" if video else "",
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)
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build_script_file = "build_" + build_name + ".sh"
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tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
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@ -200,6 +203,7 @@ class SimVerilatorToolchain:
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sim_config = None,
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coverage = False,
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opt_level = "O0",
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video = False,
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trace = False,
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trace_fst = False,
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trace_start = 0,
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@ -237,14 +241,24 @@ class SimVerilatorToolchain:
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_generate_sim_variables(platform.verilog_include_paths,
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extra_mods,
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extra_mods_path)
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extra_mods_path,
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video)
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# Generate sim config
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if sim_config:
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_generate_sim_config(sim_config)
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# Build
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_build_sim(build_name, platform.sources, jobs, threads, coverage, opt_level, trace_fst)
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_build_sim(
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build_name = build_name,
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sources = platform.sources,
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jobs = jobs,
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threads = threads,
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coverage = coverage,
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opt_level = opt_level,
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trace_fst = trace_fst,
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video = video,
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)
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# Run
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if run:
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@ -538,7 +538,7 @@ def main():
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# Video.
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if args.with_video_framebuffer or args.with_video_terminal:
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sim_config.add_module("video", "vga")
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sim_config.add_module("video", "vga")
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# SoC ------------------------------------------------------------------------------------------
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soc = SimSoC(
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@ -574,11 +574,10 @@ def main():
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generate_gtkw_savefile(builder, vns, args.trace_fst)
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builder = Builder(soc, **parser.builder_argdict)
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print(parser.builder_argdict)
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builder.build(
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sim_config = sim_config,
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interactive = not args.non_interactive,
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video = args.with_video_framebuffer or args.with_video_terminal,
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pre_run_callback = pre_run_callback,
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**parser.toolchain_argdict,
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)
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