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targets: replace MiniSoC with EthernetSoC

This commit is contained in:
Florent Kermarrec 2018-09-19 19:19:50 +02:00
parent badd992469
commit 3e77ae788f
5 changed files with 10 additions and 10 deletions
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4
litex/boards/targets/arty.py
View File

@ -114,7 +114,7 @@ class BaseSoC(SoCSDRAM):
sdram_module.timing_settings) sdram_module.timing_settings)
class MiniSoC(BaseSoC): class EthernetSoC(BaseSoC):
csr_map = { csr_map = {
"ethphy": 18, "ethphy": 18,
"ethmac": 19 "ethmac": 19
@ -161,7 +161,7 @@ def main():
help="enable Ethernet support") help="enable Ethernet support")
args = parser.parse_args() args = parser.parse_args()
cls = MiniSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()

4
litex/boards/targets/genesys2.py
View File

@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
sdram_module.timing_settings) sdram_module.timing_settings)
class MiniSoC(BaseSoC): class EthernetSoC(BaseSoC):
csr_map = { csr_map = {
"ethphy": 18, "ethphy": 18,
"ethmac": 19 "ethmac": 19
@ -143,7 +143,7 @@ def main():
help="enable Ethernet support") help="enable Ethernet support")
args = parser.parse_args() args = parser.parse_args()
cls = MiniSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()

4
litex/boards/targets/kc705.py
View File

@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
sdram_module.timing_settings) sdram_module.timing_settings)
class MiniSoC(BaseSoC): class EthernetSoC(BaseSoC):
csr_map = { csr_map = {
"ethphy": 18, "ethphy": 18,
"ethmac": 19 "ethmac": 19
@ -143,7 +143,7 @@ def main():
help="enable Ethernet support") help="enable Ethernet support")
args = parser.parse_args() args = parser.parse_args()
cls = MiniSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()

4
litex/boards/targets/nexys_video.py
View File

@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM):
sdram_module.timing_settings) sdram_module.timing_settings)
class MiniSoC(BaseSoC): class EthernetSoC(BaseSoC):
csr_map = { csr_map = {
"ethphy": 18, "ethphy": 18,
"ethmac": 19 "ethmac": 19
@ -150,7 +150,7 @@ def main():
help="enable Ethernet support") help="enable Ethernet support")
args = parser.parse_args() args = parser.parse_args()
cls = MiniSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()

4
litex/boards/targets/simple.py
View File

@ -22,7 +22,7 @@ class BaseSoC(SoCCore):
self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.crg = CRG(platform.request(platform.default_clk_name))
class MiniSoC(BaseSoC): class EthernetSoC(BaseSoC):
csr_map = { csr_map = {
"ethphy": 20, "ethphy": 20,
"ethmac": 21 "ethmac": 21
@ -62,7 +62,7 @@ def main():
platform_module = importlib.import_module(args.platform) platform_module = importlib.import_module(args.platform)
platform = platform_module.Platform() platform = platform_module.Platform()
cls = MiniSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(platform, **soc_core_argdict(args)) soc = cls(platform, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()