targets: replace MiniSoC with EthernetSoC

litex/boards/targets/arty.py

@@ -114,7 +114,7 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.timing_settings)
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 18,
         "ethmac": 19
@@ -161,7 +161,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()

litex/boards/targets/genesys2.py

@@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.timing_settings)
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 18,
         "ethmac": 19
@@ -143,7 +143,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()

litex/boards/targets/kc705.py

@@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.timing_settings)
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 18,
         "ethmac": 19
@@ -143,7 +143,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()

litex/boards/targets/nexys_video.py

@@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM):
                             sdram_module.timing_settings)
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 18,
         "ethmac": 19
@@ -150,7 +150,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()

litex/boards/targets/simple.py

@@ -22,7 +22,7 @@ class BaseSoC(SoCCore):
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
 
-class MiniSoC(BaseSoC):
+class EthernetSoC(BaseSoC):
     csr_map = {
         "ethphy": 20,
         "ethmac": 21
@@ -62,7 +62,7 @@ def main():
 
     platform_module = importlib.import_module(args.platform)
     platform = platform_module.Platform()
-    cls = MiniSoC if args.with_ethernet else BaseSoC
+    cls = EthernetSoC if args.with_ethernet else BaseSoC
     soc = cls(platform, **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()