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Fix HP slave clock source and specify AXI version 

The absence of WID signal in AXI4 when compared to AXI3 can sometimes cause problems.
This commit is contained in:
JoyBed 2024-06-16 18:50:55 +02:00 committed by Gwenhael Goavec-Merou
parent a899c23f65
commit 3f095a260d
1 changed files with 22 additions and 5 deletions
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27
litex/soc/cores/cpu/zynq7000/core.py
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@ -214,7 +214,12 @@ class Zynq7000(CPU):
def add_axi_gp_master(self):
assert len(self.axi_gp_masters) < 2
n = len(self.axi_gp_masters)
axi_gpn = axi.AXIInterface(data_width=32, address_width=32, id_width=12)
axi_gpn = axi.AXIInterface(
data_width = 32,
address_width = 32,
id_width = 12,
version = "axi3"
)
self.axi_gp_masters.append(axi_gpn)
self.cpu_params.update({
# AXI GP clk.
@ -275,7 +280,13 @@ class Zynq7000(CPU):
def add_axi_gp_slave(self, clock_domain="ps7"):
assert len(self.axi_gp_slaves) < 2
n = len(self.axi_gp_slaves)
axi_gpn = axi.AXIInterface(data_width=32, address_width=32, id_width=12, clock_domain=clock_domain)
axi_gpn = axi.AXIInterface(
data_width = 32,
address_width = 32,
id_width = 12,
version = "axi3",
clock_domain = clock_domain
)
self.axi_gp_slaves.append(axi_gpn)
self.cpu_params.update({
#AXI S GP clk.
@ -333,14 +344,20 @@ class Zynq7000(CPU):
# AXI High Performance Slave -------------------------------------------------------------------
def add_axi_hp_slave(self):
def add_axi_hp_slave(self, clock_domain="ps7"):
assert len(self.axi_hp_slaves) < 4
n = len(self.axi_hp_slaves)
axi_hpn = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
axi_hpn = axi.AXIInterface(
data_width = 64,
address_width = 32,
id_width = 6,
version = "axi3",
clock_domain = clock_domain
)
self.axi_hp_slaves.append(axi_hpn)
self.cpu_params.update({
# AXI HP0 clk.
f"i_S_AXI_HP{n}_ACLK" : ClockSignal("ps7"),
f"i_S_AXI_HP{n}_ACLK" : ClockSignal(clock_domain),
# AXI HP0 aw.
f"i_S_AXI_HP{n}_AWVALID" : axi_hpn.aw.valid,