revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)

2015-04-13 21:47:55 +02:00 · 2015-04-13 21:47:55 +02:00 · 3f15699964
parent 482486706c
commit 3f15699964
1 changed files with 1 additions and 5 deletions
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@ -178,11 +178,7 @@ def _printheader(f, ios, name, ns):
        if sig in wires:
            r += "wire " + _printsig(ns, sig) + ";\n"
        else:
-            if isinstance(sig.reset, int):
-                resetexpr = " = " + _printexpr(ns, sig.reset)[0]
-            else:
-                resetexpr = ""
-            r += "reg " + _printsig(ns, sig) + resetexpr + ";\n"
+            r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
    r += "\n"
    return r