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revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)

This commit is contained in:
Florent Kermarrec 2015-04-13 21:47:55 +02:00
parent 482486706c
commit 3f15699964
1 changed files with 1 additions and 5 deletions
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6
migen/fhdl/verilog.py
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@ -178,11 +178,7 @@ def _printheader(f, ios, name, ns):
if sig in wires: if sig in wires:
r += "wire " + _printsig(ns, sig) + ";\n" r += "wire " + _printsig(ns, sig) + ";\n"
else: else:
if isinstance(sig.reset, int): r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
resetexpr = " = " + _printexpr(ns, sig.reset)[0]
else:
resetexpr = ""
r += "reg " + _printsig(ns, sig) + resetexpr + ";\n"
r += "\n" r += "\n"
return r return r