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litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files 

We should eventually try to use python package_data or data_file for that.
This commit is contained in:
Florent Kermarrec 2015-07-22 14:13:41 +02:00
parent 84514cf8d5
commit 40740d3ddc
2 changed files with 9 additions and 10 deletions
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1
misoclib/com/litepcie/example_designs/targets/dma.py
View File

@ -69,6 +69,7 @@ class PCIeDMASoC(SoC, AutoCSR):
with_timer=False
)
self.submodules.crg = _CRG(platform)
platform.misoc_path = "../../../../"
# PCIe endpoint
self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)

18
misoclib/com/litepcie/phy/s7pciephy.py
View File

@ -151,15 +151,13 @@ class S7PCIEPHY(Module, AutoCSR):
convert_size(dcommand[12:15], self.max_request_size),
convert_size(dcommand[5:8], self.max_payload_size)
]
extcores_path = "extcores"
# XXX find a better way to do this?
current_path = os.getcwd()
current_path = current_path.replace("\\", "/")
if "litepcie/example_designs" in current_path:
extcores_path = os.path.join("..", "..", "..", "..", extcores_path)
platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "common"))
if hasattr(platform, "misoc_path"):
misoc_path = platform.misoc_path
else:
misoc_path = "./"
litepcie_phy_wrapper_path = os.path.join(misoc_path, "extcores", "litepcie_phy_wrappers")
platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "common"))
if device[:4] == "xc7k":
platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "kintex7"))
platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "kintex7"))
elif device[:4] == "xc7a":
platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "artix7"))
platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "artix7"))