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cores/dna: Add initial Ultrascale support.
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@ -63,3 +63,9 @@ class S7DNA(XilinxDNA):
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XilinxDNA.__init__(self, nbits=57, primitive="DNA_PORT", *args, **kwargs)
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class DNA(XilinxDNA): pass # Compat.
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# Xilinx Ultrascale DNA ----------------------------------------------------------------------------
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class USDNA(XilinxDNA):
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def __init__(self, *args, **kwargs):
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XilinxDNA.__init__(self, nbits=96, primitive="DNA_PORTE2", *args, **kwargs)
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