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cores/dna: Reduce default clk_divider to 2.

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To fix https://github.com/enjoy-digital/litex/issues/1516.
This commit is contained in:
Florent Kermarrec 2023-02-10 11:35:13 +01:00
parent 838719c276
commit b2053b7c52
1 changed files with 1 additions and 2 deletions
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3
litex/soc/cores/dna.py
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@ -13,11 +13,10 @@ from litex.gen import *
from litex.soc.interconnect.csr import *
# Xilinx DNA (Device Identifier) -------------------------------------------------------------------
class XilinxDNA(Module, AutoCSR):
def __init__(self, nbits=57, primitive="DNA_PORT", clk_divider=16):
def __init__(self, nbits=57, primitive="DNA_PORT", clk_divider=2):
self.nbits = nbits
self.clk_divider = clk_divider
self._id = CSRStatus(nbits)