Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #201 from gsomlo/gls-fix-initmem 

tools/litex_sim: fix default endianness for mem_init
This commit is contained in:
enjoy-digital 2019-06-19 08:32:38 +02:00 committed by GitHub
parent f47b4902e5 ab827d210d
commit 408d3f1f7c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex/tools/litex_sim.py
View File

@ -214,10 +214,10 @@ def main():
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
cpu_endianness = "big"
cpu_endianness = "little"
if "cpu_type" in soc_kwargs:
if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]:
cpu_endianness = "little"
if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
cpu_endianness = "big"
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)