Merge pull request #830 from dayjaby/vexriscv_mem_map
VexRiscv: More general mem_map
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commit
415bf63594
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@ -96,12 +96,13 @@ class VexRiscv(CPU, AutoCSR):
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io_regions = {0x80000000: 0x80000000} # origin, length
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io_regions = {0x80000000: 0x80000000} # origin, length
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@property
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@property
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def mem_map_linux(self):
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def mem_map(self):
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return {
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return {
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"rom": 0x00000000,
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"rom": 0x00000000,
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"sram": 0x10000000,
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"sram": 0x10000000,
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"main_ram": 0x40000000,
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"main_ram": 0x40000000,
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"csr": 0xf0000000,
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"csr": 0xf0000000,
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"vexriscv_debug": 0xf00f0000,
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}
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}
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@property
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@property
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@ -110,7 +111,7 @@ class VexRiscv(CPU, AutoCSR):
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flags += " -D__vexriscv__"
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flags += " -D__vexriscv__"
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return flags
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return flags
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def __init__(self, platform, variant="standard"):
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def __init__(self, platform, variant="standard", timer_enabled=True):
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self.platform = platform
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self.platform = platform
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self.variant = variant
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self.variant = variant
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self.human_name = CPU_VARIANTS.get(variant, "VexRiscv")
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self.human_name = CPU_VARIANTS.get(variant, "VexRiscv")
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@ -157,9 +158,8 @@ class VexRiscv(CPU, AutoCSR):
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i_dBusWishbone_ERR = dbus.err
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i_dBusWishbone_ERR = dbus.err
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)
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)
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if "linux" in variant:
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if timer_enabled:
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self.add_timer()
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self.add_timer()
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self.mem_map = self.mem_map_linux
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if "debug" in variant:
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if "debug" in variant:
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self.add_debug()
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self.add_debug()
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@ -267,7 +267,7 @@ class VexRiscv(CPU, AutoCSR):
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def add_soc_components(self, soc, soc_region_cls):
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def add_soc_components(self, soc, soc_region_cls):
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if "debug" in self.variant:
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if "debug" in self.variant:
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soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(origin=0xf00f0000, size=0x100, cached=False))
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soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(origin=soc.mem_map.get("vexriscv_debug"), size=0x100, cached=False))
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def use_external_variant(self, variant_filename):
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def use_external_variant(self, variant_filename):
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