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tools/litex_sim: Add boot to main_ram when sdram_init contents provided.

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This commit is contained in:
Florent Kermarrec 2021-02-25 09:10:26 +01:00
parent 8f5d2ba27f
commit 6e883b4513
1 changed files with 1 additions and 1 deletions
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2
litex/tools/litex_sim.py
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@ -448,7 +448,7 @@ def main():
trace_reset_on = trace_start > 0 or trace_end > 0,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
**soc_kwargs)
if args.ram_init is not None:
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
if args.with_ethernet:
for i in range(4):