tools/litex_sim: Disable SDRAM memtest when sdram_init contents provided.
This avoid corrupting pre-initialized contents or disabling memtest manually.
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@ -216,9 +216,13 @@ class SimSoC(SoCCore):
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = False
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)
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# Reduce memtest size for simulation speedup
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self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
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self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
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if sdram_init != []:
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# Skip SDRAM test to avoid corrupting pre-initialized contents.
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self.add_constant("SDRAM_TEST_DISABLE")
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else:
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# Reduce memtest size for simulation speedup
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self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
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self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
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#assert not (with_ethernet and with_etherbone)
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