Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

soc_core: optimize mem_decoder

Browse source 
Non-optimized version was tested on 7-series and was additional resource usage
was not noticeable. This does not seems to be the case on iCE40 (see #220), so
hand optimize it. On 256MB aligned addresses, it should be equivalent to the
old decoder used by previously in LiteX.

The only requirement is that to have address aligned on size, which was already
the case. An assertion will trigger it this condition is not respected.
This commit is contained in:
Florent Kermarrec 2019-07-22 08:53:18 +02:00
parent 0eff65bb31
commit 41eb21b343
1 changed files with 4 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
litex/soc/integration/soc_core.py
View file

@ -98,7 +98,10 @@ def get_mem_data(filename_or_regions, endianness="big", mem_size=None):
def mem_decoder(address, size=0x10000000): def mem_decoder(address, size=0x10000000):
address &= ~0x80000000 address &= ~0x80000000
return lambda a: (a[:-1] >= address//4) & (a[:-1] < (address + size)//4) assert (address & (size - 1)) == 0
address >>= 2 # bytes to words aligned
size >>= 2 # bytes to words aligned
return lambda a: (a[log2_int(size):-1] == (address >> log2_int(size)))
def csr_map_update(csr_map, csr_peripherals): def csr_map_update(csr_map, csr_peripherals):
csr_map.update(dict((n, v) csr_map.update(dict((n, v)