cores/spi_mmap: fix data in unused rx_fifo bits

clear miso at start. Prevent previous transfer data in unused bits
with 8 and 16bit slot lengths and 32bit bus read. Fixes 2 tests.

litex/soc/cores/spi/spi_mmap.py

@@ -206,7 +206,10 @@ class SPIMaster(LiteXModule):
         self.sync += [
             If(miso_shift,
                 miso_data.eq(Cat(miso, miso_data))
-            )
+            ),
+            If(self.start,
+                miso_data.eq(0)
+            ),
         ]
         self.comb += self.miso.eq(miso_data)