cores/spi_mmap: fix data in unused rx_fifo bits

clear miso at start. Prevent previous transfer data in unused bits
with 8 and 16bit slot lengths and 32bit bus read. Fixes 2 tests.
This commit is contained in:
Andrew Dennison 2024-02-25 11:13:45 +11:00
parent a9c007d8d7
commit 422b02cc16
1 changed files with 4 additions and 1 deletions

View File

@ -206,7 +206,10 @@ class SPIMaster(LiteXModule):
self.sync += [ self.sync += [
If(miso_shift, If(miso_shift,
miso_data.eq(Cat(miso, miso_data)) miso_data.eq(Cat(miso, miso_data))
) ),
If(self.start,
miso_data.eq(0)
),
] ]
self.comb += self.miso.eq(miso_data) self.comb += self.miso.eq(miso_data)