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cpu: cleanup wrappers

This commit is contained in:
Florent Kermarrec 2017-12-10 02:52:01 +01:00
parent 43429560d4
commit 4239aff68a
3 changed files with 146 additions and 131 deletions
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83
litex/soc/cores/cpu/lm32/core.py
View File

@ -11,56 +11,69 @@ class LM32(Module):
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
###
# # #
i_adr_o = Signal(32)
d_adr_o = Signal(32)
self.specials += Instance("lm32_cpu",
p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
i_clk_i=ClockSignal(),
i_rst_i=ResetSignal(),
i_clk_i=ClockSignal(),
i_rst_i=ResetSignal(),
i_interrupt=self.interrupt,
i_interrupt=self.interrupt,
o_I_ADR_O=i_adr_o,
o_I_DAT_O=i.dat_w,
o_I_SEL_O=i.sel,
o_I_CYC_O=i.cyc,
o_I_STB_O=i.stb,
o_I_WE_O=i.we,
o_I_CTI_O=i.cti,
o_I_BTE_O=i.bte,
i_I_DAT_I=i.dat_r,
i_I_ACK_I=i.ack,
i_I_ERR_I=i.err,
i_I_RTY_I=0,
o_I_ADR_O=i_adr_o,
o_I_DAT_O=i.dat_w,
o_I_SEL_O=i.sel,
o_I_CYC_O=i.cyc,
o_I_STB_O=i.stb,
o_I_WE_O=i.we,
o_I_CTI_O=i.cti,
o_I_BTE_O=i.bte,
i_I_DAT_I=i.dat_r,
i_I_ACK_I=i.ack,
i_I_ERR_I=i.err,
i_I_RTY_I=0,
o_D_ADR_O=d_adr_o,
o_D_DAT_O=d.dat_w,
o_D_SEL_O=d.sel,
o_D_CYC_O=d.cyc,
o_D_STB_O=d.stb,
o_D_WE_O=d.we,
o_D_CTI_O=d.cti,
o_D_BTE_O=d.bte,
i_D_DAT_I=d.dat_r,
i_D_ACK_I=d.ack,
i_D_ERR_I=d.err,
i_D_RTY_I=0)
o_D_ADR_O=d_adr_o,
o_D_DAT_O=d.dat_w,
o_D_SEL_O=d.sel,
o_D_CYC_O=d.cyc,
o_D_STB_O=d.stb,
o_D_WE_O=d.we,
o_D_CTI_O=d.cti,
o_D_BTE_O=d.bte,
i_D_DAT_I=d.dat_r,
i_D_ACK_I=d.ack,
i_D_ERR_I=d.err,
i_D_RTY_I=0)
self.comb += [
self.ibus.adr.eq(i_adr_o[2:]),
self.dbus.adr.eq(d_adr_o[2:])
]
# add Verilog sources
# add verilog sources
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
"lm32_cpu.v",
"lm32_instruction_unit.v",
"lm32_decoder.v",
"lm32_load_store_unit.v",
"lm32_adder.v",
"lm32_addsub.v",
"lm32_logic_op.v",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_mc_arithmetic.v",
"lm32_interrupt.v",
"lm32_ram.v",
"lm32_dp_ram.v",
"lm32_icache.v",
"lm32_dcache.v",
"lm32_debug.v",
"lm32_itlb.v",
"lm32_dtlb.v")
platform.add_verilog_include_path(vdir)

104
litex/soc/cores/cpu/mor1kx/core.py
View File

@ -11,72 +11,72 @@ class MOR1KX(Module):
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
###
# # #
i_adr_o = Signal(32)
d_adr_o = Signal(32)
self.specials += Instance("mor1kx",
p_FEATURE_INSTRUCTIONCACHE="ENABLED",
p_OPTION_ICACHE_BLOCK_WIDTH=4,
p_OPTION_ICACHE_SET_WIDTH=8,
p_OPTION_ICACHE_WAYS=1,
p_OPTION_ICACHE_LIMIT_WIDTH=31,
p_FEATURE_DATACACHE="ENABLED",
p_OPTION_DCACHE_BLOCK_WIDTH=4,
p_OPTION_DCACHE_SET_WIDTH=8,
p_OPTION_DCACHE_WAYS=1,
p_OPTION_DCACHE_LIMIT_WIDTH=31,
p_FEATURE_TIMER="NONE",
p_OPTION_PIC_TRIGGER="LEVEL",
p_FEATURE_SYSCALL="NONE",
p_FEATURE_TRAP="NONE",
p_FEATURE_RANGE="NONE",
p_FEATURE_OVERFLOW="NONE",
p_FEATURE_ADDC="ENABLED",
p_FEATURE_CMOV="ENABLED",
p_FEATURE_FFL1="ENABLED",
p_OPTION_CPU0="CAPPUCCINO",
p_OPTION_RESET_PC=reset_pc,
p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_FEATURE_INSTRUCTIONCACHE="ENABLED",
p_OPTION_ICACHE_BLOCK_WIDTH=4,
p_OPTION_ICACHE_SET_WIDTH=8,
p_OPTION_ICACHE_WAYS=1,
p_OPTION_ICACHE_LIMIT_WIDTH=31,
p_FEATURE_DATACACHE="ENABLED",
p_OPTION_DCACHE_BLOCK_WIDTH=4,
p_OPTION_DCACHE_SET_WIDTH=8,
p_OPTION_DCACHE_WAYS=1,
p_OPTION_DCACHE_LIMIT_WIDTH=31,
p_FEATURE_TIMER="NONE",
p_OPTION_PIC_TRIGGER="LEVEL",
p_FEATURE_SYSCALL="NONE",
p_FEATURE_TRAP="NONE",
p_FEATURE_RANGE="NONE",
p_FEATURE_OVERFLOW="NONE",
p_FEATURE_ADDC="ENABLED",
p_FEATURE_CMOV="ENABLED",
p_FEATURE_FFL1="ENABLED",
p_OPTION_CPU0="CAPPUCCINO",
p_OPTION_RESET_PC=reset_pc,
p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
i_clk=ClockSignal(),
i_rst=ResetSignal(),
i_clk=ClockSignal(),
i_rst=ResetSignal(),
i_irq_i=self.interrupt,
i_irq_i=self.interrupt,
o_iwbm_adr_o=i_adr_o,
o_iwbm_dat_o=i.dat_w,
o_iwbm_sel_o=i.sel,
o_iwbm_cyc_o=i.cyc,
o_iwbm_stb_o=i.stb,
o_iwbm_we_o=i.we,
o_iwbm_cti_o=i.cti,
o_iwbm_bte_o=i.bte,
i_iwbm_dat_i=i.dat_r,
i_iwbm_ack_i=i.ack,
i_iwbm_err_i=i.err,
i_iwbm_rty_i=0,
o_iwbm_adr_o=i_adr_o,
o_iwbm_dat_o=i.dat_w,
o_iwbm_sel_o=i.sel,
o_iwbm_cyc_o=i.cyc,
o_iwbm_stb_o=i.stb,
o_iwbm_we_o=i.we,
o_iwbm_cti_o=i.cti,
o_iwbm_bte_o=i.bte,
i_iwbm_dat_i=i.dat_r,
i_iwbm_ack_i=i.ack,
i_iwbm_err_i=i.err,
i_iwbm_rty_i=0,
o_dwbm_adr_o=d_adr_o,
o_dwbm_dat_o=d.dat_w,
o_dwbm_sel_o=d.sel,
o_dwbm_cyc_o=d.cyc,
o_dwbm_stb_o=d.stb,
o_dwbm_we_o=d.we,
o_dwbm_cti_o=d.cti,
o_dwbm_bte_o=d.bte,
i_dwbm_dat_i=d.dat_r,
i_dwbm_ack_i=d.ack,
i_dwbm_err_i=d.err,
i_dwbm_rty_i=0)
o_dwbm_adr_o=d_adr_o,
o_dwbm_dat_o=d.dat_w,
o_dwbm_sel_o=d.sel,
o_dwbm_cyc_o=d.cyc,
o_dwbm_stb_o=d.stb,
o_dwbm_we_o=d.we,
o_dwbm_cti_o=d.cti,
o_dwbm_bte_o=d.bte,
i_dwbm_dat_i=d.dat_r,
i_dwbm_ack_i=d.ack,
i_dwbm_err_i=d.err,
i_dwbm_rty_i=0)
self.comb += [
self.ibus.adr.eq(i_adr_o[2:]),
self.dbus.adr.eq(d_adr_o[2:])
]
# add Verilog sources
# add verilog sources
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)),
"verilog", "rtl", "verilog")

90
litex/soc/cores/cpu/picorv32/core.py
View File

@ -22,57 +22,58 @@ class PicoRV32(Module):
mem_rdata = Signal(32)
self.specials += Instance("picorv32",
p_ENABLE_COUNTERS=1,
p_ENABLE_REGS_16_31=1,
p_ENABLE_REGS_DUALPORT=1,
p_LATCHED_MEM_RDATA=0,
p_TWO_STAGE_SHIFT=1,
p_TWO_CYCLE_COMPARE=0,
p_TWO_CYCLE_ALU=0,
p_CATCH_MISALIGN=1,
p_CATCH_ILLINSN=1,
p_ENABLE_PCPI=0,
p_ENABLE_MUL=0,
p_ENABLE_IRQ=0,
p_ENABLE_IRQ_QREGS=1,
p_ENABLE_IRQ_TIMER=1,
p_MASKED_IRQ=0x00000000,
p_LATCHED_IRQ=0xffffffff,
p_PROGADDR_RESET=progaddr_reset,
p_PROGADDR_IRQ=0x00000010,
p_ENABLE_COUNTERS=1,
p_ENABLE_REGS_16_31=1,
p_ENABLE_REGS_DUALPORT=1,
p_LATCHED_MEM_RDATA=0,
p_TWO_STAGE_SHIFT=1,
p_TWO_CYCLE_COMPARE=0,
p_TWO_CYCLE_ALU=0,
p_CATCH_MISALIGN=1,
p_CATCH_ILLINSN=1,
p_ENABLE_PCPI=0,
p_ENABLE_MUL=0,
p_ENABLE_IRQ=0,
p_ENABLE_IRQ_QREGS=1,
p_ENABLE_IRQ_TIMER=1,
p_MASKED_IRQ=0x00000000,
p_LATCHED_IRQ=0xffffffff,
p_PROGADDR_RESET=progaddr_reset,
p_PROGADDR_IRQ=0x00000010,
i_clk=ClockSignal(),
i_resetn=~ResetSignal(),
i_clk=ClockSignal(),
i_resetn=~ResetSignal(),
o_mem_valid=mem_valid,
o_mem_instr=mem_instr,
i_mem_ready=mem_ready,
o_mem_valid=mem_valid,
o_mem_instr=mem_instr,
i_mem_ready=mem_ready,
o_mem_addr=mem_addr,
o_mem_wdata=mem_wdata,
o_mem_wstrb=mem_wstrb,
i_mem_rdata=mem_rdata,
o_mem_addr=mem_addr,
o_mem_wdata=mem_wdata,
o_mem_wstrb=mem_wstrb,
i_mem_rdata=mem_rdata,
o_mem_la_read=Signal(), # Not used
o_mem_la_write=Signal(), # Not used
o_mem_la_addr=Signal(32), # Not used
o_mem_la_wdata=Signal(32), # Not used
o_mem_la_wstrb=Signal(4), # Not used
o_mem_la_read=Signal(), # Not used
o_mem_la_write=Signal(), # Not used
o_mem_la_addr=Signal(32), # Not used
o_mem_la_wdata=Signal(32), # Not used
o_mem_la_wstrb=Signal(4), # Not used
o_pcpi_valid=Signal(), # Not used
o_pcpi_insn=Signal(32), # Not used
o_pcpi_rs1=Signal(32), # Not used
o_pcpi_rs2=Signal(32), # Not used
i_pcpi_wr=0,
i_pcpi_rd=0,
i_pcpi_wait=0,
i_pcpi_ready=0,
o_pcpi_valid=Signal(), # Not used
o_pcpi_insn=Signal(32), # Not used
o_pcpi_rs1=Signal(32), # Not used
o_pcpi_rs2=Signal(32), # Not used
i_pcpi_wr=0,
i_pcpi_rd=0,
i_pcpi_wait=0,
i_pcpi_ready=0,
i_irq=self.interrupt,
o_eoi=Signal(32) # Not used
)
i_irq=self.interrupt,
o_eoi=Signal(32)) # Not used
# adapt mem interface to wishbone
self.comb += [
# instruction
i.adr.eq(mem_addr[2:]),
i.dat_w.eq(mem_wdata),
i.we.eq(mem_wstrb != 0),
@ -86,6 +87,7 @@ class PicoRV32(Module):
mem_rdata.eq(i.dat_r),
),
# data
d.adr.eq(mem_addr[2:]),
d.dat_w.eq(mem_wdata),
d.we.eq(mem_wstrb != 0),
@ -100,7 +102,7 @@ class PicoRV32(Module):
)
]
# add Verilog sources
# add verilog sources
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_source(os.path.join(vdir, "picorv32.v"))