Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code

This commit is contained in:
Florent Kermarrec 2017-12-07 17:57:23 +01:00
parent 27d37fa95d
commit 43429560d4
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex/soc/integration/builder.py
View File

@ -146,7 +146,8 @@ class Builder:
self._generate_includes()
self._generate_software()
if self.soc.integrated_rom_size and self.compile_software:
self._initialize_rom()
if not self.soc.integrated_rom_initialized:
self._initialize_rom()
if self.csr_csv is not None:
self._generate_csr_csv()

5
litex/soc/integration/soc_core.py
View File

@ -61,7 +61,7 @@ class SoCCore(Module):
}
def __init__(self, platform, clk_freq,
cpu_type="lm32", cpu_reset_address=0x00000000,
integrated_rom_size=0,
integrated_rom_size=0, integrated_rom_init=[],
integrated_sram_size=4096,
integrated_main_ram_size=0, integrated_main_ram_init=[],
shadow_base=0x80000000,
@ -82,6 +82,7 @@ class SoCCore(Module):
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
@ -114,7 +115,7 @@ class SoCCore(Module):
self.config["CPU_TYPE"] = str(cpu_type).upper()
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size: