Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cpu: cleanup wrappers

This commit is contained in:
Florent Kermarrec 2017-12-10 02:52:01 +01:00
parent 43429560d4
commit 4239aff68a
3 changed files with 146 additions and 131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
litex/soc/cores/cpu/lm32/core.py
View File

@ -11,7 +11,7 @@ class LM32(Module):
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
###
# # #
i_adr_o = Signal(32)
d_adr_o = Signal(32)
@ -54,13 +54,26 @@ class LM32(Module):
self.dbus.adr.eq(d_adr_o[2:])
]
# add Verilog sources
# add verilog sources
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
"lm32_cpu.v",
"lm32_instruction_unit.v",
"lm32_decoder.v",
"lm32_load_store_unit.v",
"lm32_adder.v",
"lm32_addsub.v",
"lm32_logic_op.v",
"lm32_shifter.v",
"lm32_multiplier.v",
"lm32_mc_arithmetic.v",
"lm32_interrupt.v",
"lm32_ram.v",
"lm32_dp_ram.v",
"lm32_icache.v",
"lm32_dcache.v",
"lm32_debug.v",
"lm32_itlb.v",
"lm32_dtlb.v")
platform.add_verilog_include_path(vdir)

4
litex/soc/cores/cpu/mor1kx/core.py
View File

@ -11,7 +11,7 @@ class MOR1KX(Module):
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
###
# # #
i_adr_o = Signal(32)
d_adr_o = Signal(32)
@ -76,7 +76,7 @@ class MOR1KX(Module):
self.dbus.adr.eq(d_adr_o[2:])
]
# add Verilog sources
# add verilog sources
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)),
"verilog", "rtl", "verilog")

8
litex/soc/cores/cpu/picorv32/core.py
View File

@ -69,10 +69,11 @@ class PicoRV32(Module):
i_pcpi_ready=0,
i_irq=self.interrupt,
o_eoi=Signal(32) # Not used
)
o_eoi=Signal(32)) # Not used
# adapt mem interface to wishbone
self.comb += [
# instruction
i.adr.eq(mem_addr[2:]),
i.dat_w.eq(mem_wdata),
i.we.eq(mem_wstrb != 0),
@ -86,6 +87,7 @@ class PicoRV32(Module):
mem_rdata.eq(i.dat_r),
),
# data
d.adr.eq(mem_addr[2:]),
d.dat_w.eq(mem_wdata),
d.we.eq(mem_wstrb != 0),
@ -100,7 +102,7 @@ class PicoRV32(Module):
)
]
# add Verilog sources
# add verilog sources
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_source(os.path.join(vdir, "picorv32.v"))