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gen/fhdl/verilog: add do in reserved_keywords

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Florent Kermarrec 2016-04-26 17:13:41 +02:00
parent 80d673e502
commit 42767286ca
1 changed files with 1 additions and 1 deletions
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litex/gen/fhdl/verilog.py
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@ -27,7 +27,7 @@ _reserved_keywords = {
"specify", "specparam", "strong0", "strong1", "supply0", "supply1",
"table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0",
"tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait",
"wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor"
"wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor", "do"
}