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liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705)

This commit is contained in:
Florent Kermarrec 2015-04-12 14:27:29 +02:00
parent 93ed3212f7
commit 4329e3e1b9
1 changed files with 2 additions and 1 deletions
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3
misoclib/com/liteeth/phy/mii.py
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@ -94,7 +94,8 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset): def __init__(self, clock_pads, pads, with_hw_init_reset):
self._reset = CSRStorage() self._reset = CSRStorage()
### ###
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy) if hasattr(clock_pads, "phy"):
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain()