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soc/add_pcie: Expose with_synchronizer parameter.

This commit is contained in:
Florent Kermarrec 2022-09-01 17:46:46 +02:00
parent b24d744f8e
commit 4426e61899
1 changed files with 6 additions and 4 deletions
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4
litex/soc/integration/soc.py
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@ -1920,7 +1920,8 @@ class LiteXSoC(SoC):
def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32, def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32,
with_dma_buffering = True, dma_buffering_depth=1024, with_dma_buffering = True, dma_buffering_depth=1024,
with_dma_loopback = True, with_dma_loopback = True,
with_msi = True): with_msi = True,
with_synchronizer = False):
# Imports # Imports
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA from litepcie.frontend.dma import LitePCIeDMA
@ -1959,6 +1960,7 @@ class LiteXSoC(SoC):
dma = LitePCIeDMA(phy, endpoint, dma = LitePCIeDMA(phy, endpoint,
with_buffering = with_dma_buffering, buffering_depth=dma_buffering_depth, with_buffering = with_dma_buffering, buffering_depth=dma_buffering_depth,
with_loopback = with_dma_loopback, with_loopback = with_dma_loopback,
with_synchronizer = with_synchronizer,
address_width = address_width address_width = address_width
) )
setattr(self.submodules, f"{name}_dma{i}", dma) setattr(self.submodules, f"{name}_dma{i}", dma)