parent
18452c8193
commit
449466d5b7
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@ -1,6 +1,7 @@
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from migen.fhdl.structure import *
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from migen.fhdl.structure import *
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from migen.bus import csr
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from migen.bank import description, csrgen
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from migen.bank import description, csrgen
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from migen.bank.description import READ_ONLY, WRITE_ONLY
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from migen.bank.description import *
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class Term:
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class Term:
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def __init__(self, width, pipe=False):
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def __init__(self, width, pipe=False):
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@ -220,7 +221,7 @@ class Sum:
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return Fragment(comb=comb,sync=sync,instances=inst)
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return Fragment(comb=comb,sync=sync,instances=inst)
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class Recorder:
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class Storage:
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def __init__(self, width, depth):
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def __init__(self, width, depth):
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self.width = width
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self.width = width
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self.depth = depth
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self.depth = depth
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@ -286,7 +287,7 @@ class Recorder:
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)
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)
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]
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]
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return Fragment(comb=comb, sync=sync, memories=memories)
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return Fragment(comb=comb, sync=sync, memories=memories)
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class Sequencer:
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class Sequencer:
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def __init__(self,depth):
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def __init__(self,depth):
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self.depth = depth
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self.depth = depth
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@ -294,12 +295,14 @@ class Sequencer:
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# Controller interface
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# Controller interface
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self.ctl_rst = Signal()
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self.ctl_rst = Signal()
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self.ctl_offset = Signal(BV(self.depth_width))
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self.ctl_offset = Signal(BV(self.depth_width))
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self.ctl_size = Signal(BV(self.depth_width))
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self.ctl_arm = Signal()
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self.ctl_arm = Signal()
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self.ctl_done = Signal()
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self.ctl_done = Signal()
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# Triggers interface
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# Triggers interface
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self.trig_hit = Signal()
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self.trig_hit = Signal()
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# Recorder interface
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# Recorder interface
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self.rec_offset = Signal(BV(self.depth_width))
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self.rec_offset = Signal(BV(self.depth_width))
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self.rec_size = Signal(BV(self.depth_width))
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self.rec_start = Signal()
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self.rec_start = Signal()
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self.rec_done = Signal()
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self.rec_done = Signal()
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# Others
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# Others
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@ -320,10 +323,71 @@ class Sequencer:
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]
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]
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comb += [
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comb += [
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self.rec_offset.eq(self.ctl_offset),
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self.rec_offset.eq(self.ctl_offset),
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self.rec_start.eq(self.enable & self.trig_hit)
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self.rec_size.eq(self.ctl_size),
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self.rec_start.eq(self.enable & self.trig_hit),
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self.ctl_done.eq(~self.enable)
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]
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]
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return Fragment(comb=comb, sync=sync)
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return Fragment(comb=comb, sync=sync)
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class Recorder:
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def __init__(self,address, width, depth):
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self.address = address
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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self.storage = Storage(self.width, self.depth)
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self.sequencer = Sequencer(self.depth)
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# Csr interface
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self._rst = RegisterField("rst", reset=1)
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self._arm = RegisterField("arm", reset=0)
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self._done = RegisterField("done", reset=0, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._size = RegisterField("size", self.depth_width, reset=1)
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self._offset = RegisterField("offset", self.depth_width, reset=1)
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self._get = RegisterField("get", reset=1)
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self._get_dat = RegisterField("get_dat", self.width, reset=1,access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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regs = [self._rst, self._arm, self._done,
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self._size, self._offset,
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self._get, self._get_dat]
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self.bank = csrgen.Bank(regs,address=address)
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# Trigger Interface
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self.trig_hit = Signal()
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self.trig_dat = Signal(BV(self.width))
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def get_fragment(self):
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comb = []
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sync = []
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#Bank <--> Storage / Sequencer
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comb += [
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self.sequencer.ctl_rst.eq(self._rst.field.r),
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self.storage.rst.eq(self._rst.field.r),
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self.sequencer.ctl_offset.eq(self._offset.field.r),
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self.sequencer.ctl_size.eq(self._size.field.r),
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self.sequencer.ctl_arm.eq(self._arm.field.r),
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self._done.field.w.eq(self.sequencer.ctl_done)
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]
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#Storage <--> Sequencer <--> Trigger
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comb += [
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self.storage.offset.eq(self.sequencer.rec_offset),
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self.storage.size.eq(self.sequencer.rec_size),
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self.storage.start.eq(self.sequencer.rec_start),
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self.sequencer.rec_done.eq(self.storage.done),
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self.sequencer.trig_hit.eq(self.trig_hit),
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self.storage.put.eq(self.sequencer.enable),
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self.storage.put_dat.eq(self.trig_dat)
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]
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return self.bank.get_fragment()+\
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self.storage.get_fragment()+self.sequencer.get_fragment()+\
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Fragment(comb=comb, sync=sync)
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class MigCon:
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class MigCon:
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pass
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pass
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19
top.py
19
top.py
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@ -50,15 +50,22 @@ import migScope
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#print(v)
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#print(v)
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#
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#
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#Test Recorder
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#Test Storage
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#
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#
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#recorder = migScope.Recorder(32,1024)
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#storage = migScope.Storage(32,1024)
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#v = verilog.convert(recorder.get_fragment())
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#v = verilog.convert(storage.get_fragment())
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#print(v)
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#print(v)
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#
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#
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#Test Sequencer
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#Test Sequencer
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#
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#
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sequencer = migScope.Sequencer(1024)
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#sequencer = migScope.Sequencer(1024)
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v = verilog.convert(sequencer.get_fragment())
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#v = verilog.convert(sequencer.get_fragment())
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print(v)
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#print(v)
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#
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#Test Recorder
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#
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recorder = migScope.Recorder(0,32,1024)
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v = verilog.convert(recorder.get_fragment())
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print(v)
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