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Build your hardware, easily!
5 Commits 40 Branches 14 Tags 51 MiB
C 52.8%
Python 43.5%
Assembly 1.4%
SystemVerilog 1.3%
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Florent Kermarrec 449466d5b7 rename Recorder --> Storage 
add Recorder
 		2012-08-12 17:31:15 +02:00
migScope rename Recorder --> Storage 2012-08-12 17:31:15 +02:00
README add Readme 2012-08-12 14:41:17 +02:00
top.py rename Recorder --> Storage 2012-08-12 17:31:15 +02:00

README 

[> migScope
------------

This is a small Logic Analyser to be embedded in a Fpga design to debug internal
or external.signals.

[> Status:
Early development phase

[> Contact
E-mail: florent@enjoy-digital.fr