soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths.

This commit is contained in:
Florent Kermarrec 2024-09-09 18:18:59 +02:00
parent 5cd1a57080
commit 458e0057f2
1 changed files with 6 additions and 0 deletions

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@ -659,6 +659,12 @@ class Cache(LiteXModule):
if dw_to < dw_from and (dw_from % dw_to) != 0: if dw_to < dw_from and (dw_from % dw_to) != 0:
raise ValueError("Master data width must be a multiple of {dw}".format(dw=dw_to)) raise ValueError("Master data width must be a multiple of {dw}".format(dw=dw_to))
# Bypass.
# -------
if (cachesize == 0) and (dw_to == dw_from):
self.comb += master.connect(slave)
return
# Address Split. # Address Split.
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