sdram/module: add speedgrate note for IS42S16160 and AS4C16M16

2015-03-21 18:41:59 +01:00 · 2015-03-21 18:41:59 +01:00 · 45eb5090db
parent a560ba35bd
commit 45eb5090db
1 changed files with 2 additions and 0 deletions
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@ -49,6 +49,7 @@ class IS42S16160(SDRAMModule):
 		"nrows":	8192,
 		"ncols":	512
 	}
+	# Note: timings for -7 speedgrade (add support for others speedgrades)
 	timing_settings = {
 		"tRP":		20,
 		"tRCD":		20,
@ -85,6 +86,7 @@ class AS4C16M16(SDRAMModule):
 		"nrows":	8192,
 		"ncols":	512
 	}
+	# Note: timings for -6 speedgrade (add support for others speedgrades)
 	timing_settings = {
 		"tRP":		18,
 		"tRCD":		18,