mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
add tx_reset_fsm and rx_reset_fsm
This commit is contained in:
Florent Kermarrec
parent
c27f24c4c0
commit
45f7f8aff5
3 changed files with 137 additions and 63 deletions
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@ -13,16 +13,28 @@ class K7SATAPHY(Module):
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self.sink = Sink([("d", 32)], True)
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self.source = Source([("d", 32)], True)
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# GTX
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gtx = K7SATAPHYGTX(pads, "SATA3")
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self.comb += [
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gtx.rxrate.eq(0b000),
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gtx.txrate.eq(0b000),
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]
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clocking = K7SATAPHYCRG(pads, gtx, clk_freq)
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self.submodules += gtx
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# CRG / CTRL
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crg = K7SATAPHYCRG(pads, gtx, clk_freq)
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if host:
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ctrl = K7SATAPHYHostCtrl(gtx)
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else:
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ctrl = K7SATAPHYDeviceCtrl(gtx)
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self.submodules += crg, ctrl
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self.comb += ctrl.start.eq(crg.ready)
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# DATAPATH
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rxalign = K7SATAPHYRXAlign()
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rxconvert = K7SATAPHYRXConvert()
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txconvert = K7SATAPHYTXConvert()
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self.submodules += gtx, clocking, rxalign, rxconvert, txconvert
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self.submodules += rxalign, rxconvert, txconvert
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self.comb += [
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rxalign.rxdata_i.eq(gtx.rxdata),
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rxalign.rxcharisk_i.eq(gtx.rxcharisk),
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@ -33,13 +45,8 @@ class K7SATAPHY(Module):
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gtx.txcharisk.eq(txconvert.txcharisk)
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]
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if host:
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ctrl = K7SATAPHYHostCtrl(gtx)
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else:
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ctrl = K7SATAPHYDeviceCtrl(gtx)
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self.submodules += ctrl
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self.comb += [
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If(ctrl.link_up,
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If(ctrl.ready,
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txconvert.sink.stb.eq(self.sink.stb),
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txconvert.sink.data.eq(self.sink.d),
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txconvert.sink.charisk.eq(0),
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@ -27,6 +27,7 @@ class K7SATAPHYReconfig(Module):
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class K7SATAPHYCRG(Module):
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def __init__(self, pads, gtx, clk_freq):
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self.reset = Signal()
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self.ready = Signal()
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self.clock_domains.cd_sata_tx = ClockDomain()
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self.clock_domains.cd_sata_rx = ClockDomain()
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@ -79,7 +80,6 @@ class K7SATAPHYCRG(Module):
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p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o,
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),
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Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
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Instance("BUFG", i_I=mmcm_clk1_o, o_O=self.cd_sata.clk),
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]
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self.comb += [
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gtx.txusrclk.eq(self.cd_sata_tx.clk),
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@ -98,7 +98,7 @@ class K7SATAPHYCRG(Module):
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gtx.rxusrclk2.eq(self.cd_sata_rx.clk)
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]
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# TX buffer bypass logic
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# Bypass TX buffer
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self.comb += [
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gtx.txphdlyreset.eq(0),
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gtx.txphalignen.eq(0),
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@ -107,7 +107,7 @@ class K7SATAPHYCRG(Module):
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gtx.txphinit.eq(0)
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]
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# RX buffer bypass logic
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# Bypass RX buffer
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self.comb += [
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gtx.rxphdlyreset.eq(0),
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gtx.rxdlyen.eq(0),
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@ -115,7 +115,6 @@ class K7SATAPHYCRG(Module):
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gtx.rxphalignen.eq(0),
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]
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# Configuration Reset
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# After configuration, GTX resets have to stay low for at least 500ns
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# See AR43482
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@ -126,57 +125,111 @@ class K7SATAPHYCRG(Module):
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self.sync += If(~reset_en, reset_en_cnt.eq(reset_en_cnt-1))
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self.comb += reset_en.eq(reset_en_cnt == 0)
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# once channel TX is reseted, reset TX buffer
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txbuffer_reseted = Signal()
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self.sync += \
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If(gtx.txresetdone,
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If(~txbuffer_reseted,
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gtx.txdlysreset.eq(1),
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txbuffer_reseted.eq(1)
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).Else(
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gtx.txdlysreset.eq(0)
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)
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# TX Reset FSM
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tx_reset_fsm = FSM(reset_state="IDLE")
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self.submodules += tx_reset_fsm
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tx_reset_fsm.act("IDLE",
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gtx.txuserrdy.eq(0),
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gtx.gttxreset.eq(0),
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gtx.txdlysreset.eq(0),
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If(reset_en,
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NextState("RESET_ALL"),
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)
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# once channel RX is reseted, reset RX buffer
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rxbuffer_reseted = Signal()
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self.sync += \
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If(gtx.rxresetdone,
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If(~rxbuffer_reseted,
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gtx.rxdlysreset.eq(1),
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rxbuffer_reseted.eq(1)
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).Else(
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gtx.rxdlysreset.eq(0)
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)
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)
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tx_reset_fsm.act("RESET_ALL",
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gtx.txuserrdy.eq(0),
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gtx.gttxreset.eq(1),
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gtx.txdlysreset.eq(1),
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If(gtx.cplllock & mmcm_locked,
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NextState("RELEASE_GTXRESET")
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)
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# Reset
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# initial reset generation
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rst_cnt = Signal(8)
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rst_cnt_done = Signal()
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self.sync += \
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If(~rst_cnt_done,
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rst_cnt.eq(rst_cnt+1)
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)
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tx_reset_fsm.act("RELEASE_GTXRESET",
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gtx.txuserrdy.eq(1),
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gtx.gttxreset.eq(0),
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gtx.txdlysreset.eq(1),
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If(self.reset,
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NextState("RESET_ALL")
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).Elif(gtx.txresetdone,
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NextState("RELEASE_DLYRESET")
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)
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self.comb += rst_cnt_done.eq(rst_cnt==255)
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)
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tx_reset_fsm.act("RELEASE_DLYRESET",
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gtx.txuserrdy.eq(1),
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gtx.gttxreset.eq(0),
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gtx.txdlysreset.eq(0),
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If(self.reset,
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NextState("RESET_ALL")
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).Elif(gtx.txdlysresetdone,
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NextState("READY")
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)
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)
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tx_reset_fsm.act("READY",
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gtx.txuserrdy.eq(1),
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gtx.gttxreset.eq(0),
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gtx.txdlysreset.eq(0),
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If(self.reset,
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NextState("RESET_ALL")
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)
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)
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self.comb += [
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# GTXE2
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gtx.rxuserrdy.eq(gtx.cplllock),
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gtx.txuserrdy.eq(gtx.cplllock),
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# TX
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gtx.gttxreset.eq(reset_en & (self.reset | ~gtx.cplllock)),
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# RX
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gtx.gtrxreset.eq(reset_en & (self.reset | ~gtx.cplllock)),
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# PLL
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gtx.cpllreset.eq(self.reset | ~reset_en)
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]
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# SATA TX/RX clock domains
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# RX Reset FSM
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rx_reset_fsm = FSM(reset_state="IDLE")
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self.submodules += rx_reset_fsm
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rx_reset_fsm.act("IDLE",
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gtx.rxuserrdy.eq(0),
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gtx.gtrxreset.eq(0),
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gtx.rxdlysreset.eq(0),
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If(reset_en,
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NextState("RESET_ALL"),
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)
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)
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rx_reset_fsm.act("RESET_ALL",
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gtx.rxuserrdy.eq(0),
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gtx.gtrxreset.eq(1),
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gtx.rxdlysreset.eq(1),
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If(gtx.cplllock & mmcm_locked,
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NextState("RELEASE_GTXRESET")
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)
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)
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rx_reset_fsm.act("RELEASE_GTXRESET",
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gtx.rxuserrdy.eq(1),
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gtx.gtrxreset.eq(0),
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gtx.rxdlysreset.eq(1),
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If(self.reset,
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NextState("RESET_ALL")
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).Elif(gtx.rxresetdone,
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NextState("RELEASE_DLYRESET")
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)
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)
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rx_reset_fsm.act("RELEASE_DLYRESET",
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gtx.rxuserrdy.eq(1),
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gtx.gtrxreset.eq(0),
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gtx.rxdlysreset.eq(0),
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If(self.reset,
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NextState("RESET_ALL")
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).Elif(gtx.rxdlysresetdone,
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NextState("READY")
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)
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)
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rx_reset_fsm.act("READY",
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gtx.rxuserrdy.eq(1),
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gtx.gtrxreset.eq(0),
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gtx.rxdlysreset.eq(0),
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If(self.reset,
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NextState("RESET_ALL")
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)
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)
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self.comb += self.ready.eq(tx_reset_fsm.ongoing("READY") & rx_reset_fsm.ongoing("READY"))
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# Reset PLL
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self.comb += gtx.cpllreset.eq(self.reset | ~reset_en)
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# Reset for SATA TX/RX clock domains
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self.specials += [
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AsyncResetSynchronizer(self.cd_sata_tx, ~mmcm_locked | ~gtx.txresetdone),
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AsyncResetSynchronizer(self.cd_sata_rx, ~gtx.cplllock | ~gtx.rxphaligndone),
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AsyncResetSynchronizer(self.cd_sata, ResetSignal("sata_tx") | ResetSignal("sata_rx")),
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AsyncResetSynchronizer(self.cd_sata_tx, ~self.ready),
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AsyncResetSynchronizer(self.cd_sata_rx, ~self.ready),
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]
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# Dynamic Reconfiguration
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@ -20,7 +20,8 @@ def us(t, speed="SATA3"):
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class K7SATAPHYHostCtrl(Module):
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def __init__(self, gtx):
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self.link_up = Signal()
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self.start = Signal()
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self.ready = Signal()
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self.speed = Signal(3)
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self.txdata = Signal(32)
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@ -40,6 +41,12 @@ class K7SATAPHYHostCtrl(Module):
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self.submodules += fsm
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fsm.act("RESET",
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gtx.txelecidle.eq(1),
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If(self.start,
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NextState("COMINIT")
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)
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)
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fsm.act("COMINIT",
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txcominit.eq(1),
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gtx.txelecidle.eq(1),
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If(gtx.txcomfinish & ~gtx.rxcominitdet,
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@ -114,7 +121,7 @@ class K7SATAPHYHostCtrl(Module):
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If(gtx.rxelecidle,
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NextState("RESET")
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),
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self.link_up.eq(1)
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self.ready.eq(1)
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)
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txcominit_d = Signal()
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@ -166,7 +173,8 @@ class K7SATAPHYHostCtrl(Module):
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class K7SATAPHYDeviceCtrl(Module):
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def __init__(self, gtx):
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self.link_up = Signal()
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self.start = Signal()
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self.ready = Signal()
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self.speed = Signal(3)
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self.txdata = Signal(32)
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@ -185,6 +193,12 @@ class K7SATAPHYDeviceCtrl(Module):
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self.submodules += fsm
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fsm.act("RESET",
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gtx.txelecidle.eq(1),
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If(self.start,
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NextState("AWAIT_COMINIT")
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)
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)
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fsm.act("AWAIT_COMINIT",
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gtx.txelecidle.eq(1),
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If(gtx.rxcominitdet,
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NextState("COMINIT")
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@ -241,7 +255,7 @@ class K7SATAPHYDeviceCtrl(Module):
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If(gtx.rxelecidle,
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NextState("RESET")
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),
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self.link_up.eq(1)
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self.ready.eq(1)
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)
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fsm.act("ERROR",
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gtx.txelecidle.eq(1),
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