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gen/fhdl/verilog: Ensure top is not None to build hierarchy.

This commit is contained in:
Florent Kermarrec 2023-11-08 16:57:21 +01:00
parent 862a0dbbbf
commit 4610713797
1 changed files with 10 additions and 7 deletions
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17
litex/gen/fhdl/verilog.py
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@ -90,13 +90,16 @@ def _generate_timescale(time_unit="1ns", time_precision="1ps"):
# ------------------------------------------------------------------------------------------------ #
def _generate_hierarchy(top):
hierarchy_explorer = LiteXHierarchyExplorer(top=top, depth=None, with_colors=False)
r = "/*\n"
for l in hierarchy_explorer.get_hierarchy().split("\n"):
r += l + "\n"
r = r[:-1]
r += "*/\n"
return r
if top is None:
return ""
else:
hierarchy_explorer = LiteXHierarchyExplorer(top=top, depth=None, with_colors=False)
r = "/*\n"
for l in hierarchy_explorer.get_hierarchy().split("\n"):
r += l + "\n"
r = r[:-1]
r += "*/\n"
return r
# ------------------------------------------------------------------------------------------------ #
# RESERVED KEYWORDS #