gen/fhdl/verilog: Ensure top is not None to build hierarchy.

litex/gen/fhdl/verilog.py

@@ -90,6 +90,9 @@ def _generate_timescale(time_unit="1ns", time_precision="1ps"):
 # ------------------------------------------------------------------------------------------------ #
 
 def _generate_hierarchy(top):
+    if top is None:
+        return ""
+    else:
         hierarchy_explorer = LiteXHierarchyExplorer(top=top, depth=None, with_colors=False)
         r = "/*\n"
         for l in hierarchy_explorer.get_hierarchy().split("\n"):