Merge pull request #1229 from smunaut/jtag-zynq-usp

cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
2022-03-02 21:56:03 +01:00 · 2022-03-02 21:56:03 +01:00 · 46361db135
parent 4bc1691487 d8df6cb27d
commit 46361db135
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/jtag.py
+++ b/litex/soc/cores/jtag.py
@ -308,7 +308,7 @@ class XilinxJTAG(Module):
        prim_dict = {
            # Primitive Name   Ðevice (startswith)
            "BSCAN_SPARTAN6" : ["xc6"],
-            "BSCANE2"        : ["xc7", "xcku", "xcvu"],
+            "BSCANE2"        : ["xc7", "xcku", "xcvu", "xczu"],
        }
        for prim, prim_devs in prim_dict.items():
            for prim_dev in prim_devs: