Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1229 from smunaut/jtag-zynq-usp 

cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
This commit is contained in:
enjoy-digital 2022-03-02 21:56:03 +01:00 committed by GitHub
parent 4bc1691487 d8df6cb27d
commit 46361db135
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/cores/jtag.py
View File

@ -308,7 +308,7 @@ class XilinxJTAG(Module):
prim_dict = { prim_dict = {
# Primitive Name Ðevice (startswith) # Primitive Name Ðevice (startswith)
"BSCAN_SPARTAN6" : ["xc6"], "BSCAN_SPARTAN6" : ["xc6"],
"BSCANE2" : ["xc7", "xcku", "xcvu"], "BSCANE2" : ["xc7", "xcku", "xcvu", "xczu"],
} }
for prim, prim_devs in prim_dict.items(): for prim, prim_devs in prim_dict.items():
for prim_dev in prim_devs: for prim_dev in prim_devs: