integration/soc Add accessible_region to add_memory_buses
Enables CPUs to know which memory addresses are accessible via the connected memory_bus.
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@ -396,7 +396,7 @@ class NaxRiscv(CPU):
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)
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soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
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def add_memory_buses(self, address_width, data_width):
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def add_memory_buses(self, address_width, data_width, accessible_region):
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nax_data_width = 64
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nax_burst_size = 64
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assert data_width >= nax_data_width # FIXME: Only supporting up-conversion for now.
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@ -460,6 +460,10 @@ class NaxRiscv(CPU):
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i_ram_dbus_rresp = dbus.r.resp,
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i_ram_dbus_rlast = dbus.r.last,
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)
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self.scala_args.append('mem-region-origin=0x{accessible_region.origin:x}'
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.format(accessible_region=accessible_region))
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self.scala_args.append('mem-region-length=0x{accessible_region.size:x}'
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.format(accessible_region=accessible_region))
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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@ -430,7 +430,7 @@ class VexRiscvSMP(CPU):
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)
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soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
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def add_memory_buses(self, address_width, data_width):
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def add_memory_buses(self, address_width, data_width, accessible_region):
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VexRiscvSMP.litedram_width = data_width
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from litedram.common import LiteDRAMNativePort
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@ -1460,13 +1460,16 @@ class LiteXSoC(SoC):
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sdram_size = min(sdram_size, size)
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# Add SDRAM region.
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self.bus.add_region("main_ram", SoCRegion(origin=self.mem_map.get("main_ram", origin), size=sdram_size))
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main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin),
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size=sdram_size)
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self.bus.add_region("main_ram", main_ram_region)
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# Add CPU's direct memory buses (if not already declared) ----------------------------------
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if hasattr(self.cpu, "add_memory_buses"):
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self.cpu.add_memory_buses(
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address_width = 32,
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data_width = sdram.crossbar.controller.data_width
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address_width = 32,
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data_width = sdram.crossbar.controller.data_width,
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accessible_region = main_ram_region
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)
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# Connect CPU's direct memory buses to LiteDRAM --------------------------------------------
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