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integration/soc/sdcard: add mode parameter to enable read only, write only or read+write modes.

This commit is contained in:
Florent Kermarrec 2020-07-10 11:18:22 +02:00
parent b7e4507686
commit 468db3cf08
3 changed files with 23 additions and 13 deletions
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25
litex/soc/integration/soc.py
View File

@ -1244,7 +1244,8 @@ class LiteXSoC(SoC):
self.add_csr(name) self.add_csr(name)
# Add SDCard ----------------------------------------------------------------------------------- # Add SDCard -----------------------------------------------------------------------------------
def add_sdcard(self, name="sdcard", use_emulator=False): def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False):
assert mode in ["read", "write", "read+write"]
# Imports # Imports
from litesdcard.emulator import SDEmulator from litesdcard.emulator import SDEmulator
from litesdcard.phy import SDPHY from litesdcard.phy import SDPHY
@ -1266,15 +1267,17 @@ class LiteXSoC(SoC):
self.add_csr("sdcore") self.add_csr("sdcore")
# Block2Mem DMA # Block2Mem DMA
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width) if "read" in mode:
self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness) bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.comb += self.sdcore.source.connect(self.sdblock2mem.sink) self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
self.bus.add_master("sdblock2mem", master=bus) self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
self.add_csr("sdblock2mem") self.bus.add_master("sdblock2mem", master=bus)
self.add_csr("sdblock2mem")
# Mem2Block DMA # Mem2Block DMA
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width) if "write" in mode:
self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness) bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.comb += self.sdmem2block.source.connect(self.sdcore.sink) self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
self.bus.add_master("sdmem2block", master=bus) self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
self.add_csr("sdmem2block") self.bus.add_master("sdmem2block", master=bus)
self.add_csr("sdmem2block")

4
litex/soc/software/bios/cmds/cmd_litesdcard.c
View File

@ -27,7 +27,7 @@ define_command(sdinit, sdcard_init, "Initialize SDCard", LITESDCARD_CMDS);
* Perform SDcard block read * Perform SDcard block read
* *
*/ */
#ifdef CSR_SDCORE_BASE #ifdef CSR_SDBLOCK2MEM_BASE
static void sdread(int nb_params, char **params) static void sdread(int nb_params, char **params)
{ {
unsigned int block; unsigned int block;
@ -58,7 +58,7 @@ define_command(sdread, sdread, "Read SDCard block", LITESDCARD_CMDS);
* Perform SDcard block write * Perform SDcard block write
* *
*/ */
#ifdef CSR_SDCORE_BASE #ifdef CSR_SDMEM2BLOCK_BASE
static void sdwrite(int nb_params, char **params) static void sdwrite(int nb_params, char **params)
{ {
int i; int i;

7
litex/soc/software/liblitesdcard/sdcard.c
View File

@ -555,6 +555,8 @@ int sdcard_init(void) {
return 1; return 1;
} }
#ifdef CSR_SDBLOCK2MEM_BASE
void sdcard_read(uint32_t sector, uint32_t count, uint8_t* buf) void sdcard_read(uint32_t sector, uint32_t count, uint8_t* buf)
{ {
/* Initialize DMA Writer */ /* Initialize DMA Writer */
@ -581,6 +583,10 @@ sdcard_set_block_count(count);
#endif #endif
} }
#endif
#ifdef CSR_SDMEM2BLOCK_BASE
void sdcard_write(uint32_t sector, uint32_t count, uint8_t* buf) void sdcard_write(uint32_t sector, uint32_t count, uint8_t* buf)
{ {
while (count--) { while (count--) {
@ -606,6 +612,7 @@ void sdcard_write(uint32_t sector, uint32_t count, uint8_t* buf)
sector += 1; sector += 1;
} }
} }
#endif
/*-----------------------------------------------------------------------*/ /*-----------------------------------------------------------------------*/
/* SDCard FatFs disk functions */ /* SDCard FatFs disk functions */