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Set TX UART pin high on reset 

Without this we get corrupted data on the output after
SoC reset. It was present there, but got removed in
908e72e65b refactor.
Fixes #991
This commit is contained in:
Michal Sieron 2021-08-26 18:07:03 +02:00
parent 78c1751c47
commit 47291e07f7
1 changed files with 2 additions and 0 deletions
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2
litex/soc/cores/uart.py
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@ -57,6 +57,8 @@ class RS232PHYTX(Module):
# # # # # #
pads.tx.reset = 1
data = Signal(8, reset_less=True) data = Signal(8, reset_less=True)
count = Signal(4, reset_less=True) count = Signal(4, reset_less=True)