Set TX UART pin high on reset

Without this we get corrupted data on the output after
SoC reset. It was present there, but got removed in
908e72e65b refactor.
Fixes #991

litex/soc/cores/uart.py

@@ -57,6 +57,8 @@ class RS232PHYTX(Module):
 
         # # #
 
+        pads.tx.reset = 1
+
         data  = Signal(8, reset_less=True)
         count = Signal(4, reset_less=True)