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soc/intregation: fix cpu name in logging 

Fixed CPU name being reported as irq name in logging.

```
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU noirq adding DMA Bus.
INFO:SoCDMABusHandler:Creating Bus Handler...
```
This commit is contained in:
Andrew Dennison 2023-09-02 11:40:58 +10:00
parent 57faa9102f
commit 48ab96fd43
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc.py
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@ -1113,8 +1113,8 @@ class SoC(LiteXModule, SoCCoreCompat):
self.irq.enable() self.irq.enable()
if hasattr(self.cpu, "reserved_interrupts"): if hasattr(self.cpu, "reserved_interrupts"):
self.cpu.interrupts.update(self.cpu.reserved_interrupts) self.cpu.interrupts.update(self.cpu.reserved_interrupts)
for name, loc in self.cpu.interrupts.items(): for irq_name, loc in self.cpu.interrupts.items():
self.irq.add(name, loc) self.irq.add(irq_name, loc)
self.add_config("CPU_HAS_INTERRUPT") self.add_config("CPU_HAS_INTERRUPT")
# Create optional DMA Bus (for Cache Coherence). # Create optional DMA Bus (for Cache Coherence).