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integration/soc/add_uart: pass fifo_depth to UARTCrossover.

This commit is contained in:
Florent Kermarrec 2020-12-10 14:33:29 +01:00
parent 1976fd4b90
commit 48dc574703
1 changed files with 3 additions and 1 deletions
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4
litex/soc/integration/soc.py
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@ -1096,7 +1096,9 @@ class LiteXSoC(SoC):
# Crossover
elif name in ["crossover"]:
self.submodules.uart = uart.UARTCrossover()
self.submodules.uart = uart.UARTCrossover(
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth)
# Model/Sim
elif name in ["model", "sim"]: