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Merge pull request #165 from xobs/vexriscv-cpu-reset-address 

Vexriscv cpu reset address
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enjoy-digital 2019-04-19 19:16:16 +02:00 committed by GitHub
parent ca6065a6a1 c780fb22b7
commit 49fd93ae83
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1 changed files with 2 additions and 1 deletions
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litex/soc/cores/cpu/vexriscv/core.py
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@ -24,6 +24,7 @@ class VexRiscv(Module, AutoCSR):
self.reset = Signal() self.reset = Signal()
self.ibus = ibus = wishbone.Interface() self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface() self.dbus = dbus = wishbone.Interface()
self.cpu_reset_address = cpu_reset_address
self.interrupt = Signal(32) self.interrupt = Signal(32)
@ -31,7 +32,7 @@ class VexRiscv(Module, AutoCSR):
i_clk=ClockSignal(), i_clk=ClockSignal(),
i_reset=ResetSignal() | self.reset, i_reset=ResetSignal() | self.reset,
i_externalResetVector=cpu_reset_address, i_externalResetVector=self.cpu_reset_address,
i_externalInterruptArray=self.interrupt, i_externalInterruptArray=self.interrupt,
i_timerInterrupt=0, i_timerInterrupt=0,