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integration/soc/add_sdram: Directly use main_ram mem_map mapping if available.

This commit is contained in:
Florent Kermarrec 2021-03-29 11:22:31 +02:00
parent 99a26fc710
commit 4a29e2403c
1 changed files with 2 additions and 2 deletions
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litex/soc/integration/soc.py
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@ -1192,7 +1192,7 @@ class LiteXSoC(SoC):
self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone) self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)
# Add SDRAM ------------------------------------------------------------------------------------ # Add SDRAM ------------------------------------------------------------------------------------
def add_sdram(self, name, phy, module, origin, size=None, with_bist=False, with_soc_interconnect=True, def add_sdram(self, name, phy, module, origin=None, size=None, with_bist=False, with_soc_interconnect=True,
l2_cache_size = 8192, l2_cache_size = 8192,
l2_cache_min_data_width = 128, l2_cache_min_data_width = 128,
l2_cache_reverse = True, l2_cache_reverse = True,
@ -1250,7 +1250,7 @@ class LiteXSoC(SoC):
sdram_size = min(sdram_size, size) sdram_size = min(sdram_size, size)
# Add SDRAM region. # Add SDRAM region.
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) self.bus.add_region("main_ram", SoCRegion(origin=self.mem_map.get("main_ram", origin), size=sdram_size))
# Add CPU's direct memory buses (if not already declared) ---------------------------------- # Add CPU's direct memory buses (if not already declared) ----------------------------------
if hasattr(self.cpu, "add_memory_buses"): if hasattr(self.cpu, "add_memory_buses"):