modularize SoC integration
This commit is contained in:
parent
4c50923cdf
commit
4a3a1d02e9
4
make.py
4
make.py
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@ -4,14 +4,14 @@ import argparse, os, importlib, subprocess
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from mibuild.tools import write_to_file
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from misoclib import cpuif
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from misoclib.gensoc import cpuif
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from misoclib.s6ddrphy import initsequence
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import top, jtag
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def build(platform_name, build_bitstream, build_header, csr_csv_filename, *soc_args, **soc_kwargs):
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platform_module = importlib.import_module("mibuild.platforms."+platform_name)
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platform = platform_module.Platform()
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soc = top.SoC(platform, platform_name, *soc_args, **soc_kwargs)
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soc = top.SoC(platform, *soc_args, **soc_kwargs)
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platform.add_platform_command("""
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INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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@ -0,0 +1,128 @@
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from operator import itemgetter
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from collections import defaultdict
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from math import ceil
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from migen.fhdl.std import *
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from migen.bank import csrgen
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from migen.bus import wishbone, csr, lasmibus, dfi
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from migen.bus import wishbone2lasmi, wishbone2csr
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from misoclib import lm32, uart, dfii, lasmicon, identifier, timer, memtest
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class GenSoC(Module):
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csr_base = 0xe0000000
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csr_map = {
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"crg": 0, # user
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"uart": 1, # provided
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"identifier": 2, # provided
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"timer0": 3, # provided
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"buttons": 4, # user
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"leds": 5, # user
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}
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interrupt_map = {
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"uart": 0,
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"timer0": 1,
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}
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known_platform_id = defaultdict(lambda: 0x554E, {
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"mixxeo": 0x4D58,
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"m1": 0x4D31
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})
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def __init__(self, platform, clk_freq, sram_size, l2_size=0):
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self.clk_freq = clk_freq
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self.sram_size = sram_size
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self.l2_size = l2_size
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# Wishbone
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self.submodules.cpu = lm32.LM32()
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self.submodules.sram = wishbone.SRAM(sram_size)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
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# rom 0x00000000 (shadow @0x80000000) user
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# SRAM/debug 0x10000000 (shadow @0x90000000) provided
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# CSR bridge 0x60000000 (shadow @0xe0000000) provided
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self._wb_masters = [self.cpu.ibus, self.cpu.dbus]
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self._wb_slaves = [
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(lambda a: a[26:29] == 1, self.sram.bus),
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(lambda a: a[27:29] == 3, self.wishbone2csr.wishbone)
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]
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# CSR
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self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
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self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform.name], int(clk_freq),
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log2_int(l2_size) if l2_size else 0)
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self.submodules.timer0 = timer.Timer()
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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# Interrupts
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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if hasattr(self, k):
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self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
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def ns(self, t, margin=True):
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clk_period_ns = 1000000000/self.clk_freq
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if margin:
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t += clk_period_ns/2
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return ceil(t/clk_period_ns)
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class SDRAMSoC(GenSoC):
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csr_map = {
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"dfii": 6,
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"lasmicon": 7,
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"memtest_w": 8,
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"memtest_r": 9
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}
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csr_map.update(GenSoC.csr_map)
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def __init__(self, platform, clk_freq, sram_size, l2_size, with_memtest):
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GenSoC.__init__(self, platform, clk_freq, sram_size, l2_size)
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self.with_memtest = with_memtest
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self._sdram_modules_created = False
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def create_sdram_modules(self, phy_dfi, phy_settings, sdram_geom, sdram_timing):
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if self._sdram_modules_created:
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raise FinalizeError
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self._sdram_modules_created = True
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# DFI
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self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
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phy_settings.dfi_d, phy_settings.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy_dfi)
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# LASMI
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self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits)
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if self.with_memtest:
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self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master())
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# Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000)
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
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self.add_wb_slave(lambda a: a[27:29] == 2, self.wishbone2lasmi.wishbone)
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def do_finalize(self):
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if not self._sdram_modules_created:
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raise FinalizeError("Need to call SDRAMSoC.create_sdram_modules()")
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GenSoC.do_finalize(self)
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213
top.py
213
top.py
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@ -1,46 +1,12 @@
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from fractions import Fraction
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from math import ceil
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from operator import itemgetter
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from collections import defaultdict
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from migen.fhdl.std import *
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from migen.bus import wishbone, csr, lasmibus, dfi
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from migen.bus import wishbone2lasmi, wishbone2csr
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from migen.bank import csrgen
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from mibuild.generic_platform import ConstraintError
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from misoclib import mxcrg, lm32, norflash, uart, s6ddrphy, dfii, lasmicon, \
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identifier, timer, minimac3, framebuffer, dvisampler, gpio, memtest
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from misoclib import lasmicon, mxcrg, norflash, s6ddrphy, minimac3, framebuffer, dvisampler, gpio
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from misoclib.gensoc import SDRAMSoC
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clk_freq = (83 + Fraction(1, 3))*1000000
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sram_size = 4096 # in bytes
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l2_size = 8192 # in bytes
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clk_period_ns = 1000000000/clk_freq
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def ns(t, margin=True):
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if margin:
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t += clk_period_ns/2
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return ceil(t/clk_period_ns)
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sdram_geom = lasmicon.GeomSettings(
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bank_a=2,
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row_a=13,
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col_a=10
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)
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sdram_timing = lasmicon.TimingSettings(
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tRP=ns(15),
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tRCD=ns(15),
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tWR=ns(15),
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tWTR=2,
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tREFI=ns(7800, False),
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tRFC=ns(70),
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req_queue_size=8,
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read_time=32,
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write_time=16
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)
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class MXClockPads:
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class _MXClockPads:
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def __init__(self, platform):
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self.clk50 = platform.request("clk50")
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self.trigger_reset = 0
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@ -57,129 +23,96 @@ class MXClockPads:
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self.eth_rx_clk = eth_clocks.rx
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self.eth_tx_clk = eth_clocks.tx
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class SoC(Module):
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csr_base = 0xe0000000
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class MiniSoC(SDRAMSoC):
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csr_map = {
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"crg": 0,
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"uart": 1,
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"dfii": 2,
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"identifier": 3,
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"timer0": 4,
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"minimac": 5,
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"fb": 6,
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"lasmicon": 7,
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"dvisampler0": 8,
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"dvisampler0_edid_mem": 9,
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"dvisampler1": 10,
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"dvisampler1_edid_mem": 11,
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"pots": 12,
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"buttons": 13,
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"leds": 14,
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"memtest_w": 15,
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"memtest_r": 16
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"minimac": 10,
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"fb": 11,
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"dvisampler0": 12,
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"dvisampler0_edid_mem": 13,
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"dvisampler1": 14,
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"dvisampler1_edid_mem": 15,
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}
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csr_map.update(SDRAMSoC.csr_map)
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interrupt_map = {
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"uart": 0,
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"timer0": 1,
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"minimac": 2,
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"dvisampler0": 3,
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"dvisampler1": 4,
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}
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known_platform_id = defaultdict(lambda: 0x554E, {
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"mixxeo": 0x4D58,
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"m1": 0x4D31
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})
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interrupt_map.update(SDRAMSoC.interrupt_map)
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def __init__(self, platform, platform_name, with_memtest):
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#
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# DFI
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#
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", nphases=2, cl=3, rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
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self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
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self.ddrphy.phy_settings.dfi_d, self.ddrphy.phy_settings.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, self.ddrphy.dfi)
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def __init__(self, platform, with_memtest):
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SDRAMSoC.__init__(self, platform,
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clk_freq=(83 + Fraction(1, 3))*1000000,
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sram_size=4096,
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l2_size=8192,
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with_memtest=with_memtest)
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#
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# LASMI
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#
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self.submodules.lasmicon = lasmicon.LASMIcon(self.ddrphy.phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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sdram_geom = lasmicon.GeomSettings(
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bank_a=2,
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row_a=13,
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col_a=10
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)
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sdram_timing = lasmicon.TimingSettings(
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tRP=self.ns(15),
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tRCD=self.ns(15),
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tWR=self.ns(15),
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tWTR=2,
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tREFI=self.ns(7800, False),
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tRFC=self.ns(70),
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self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits)
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lasmim_wb = self.lasmixbar.get_master()
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if platform_name == "mixxeo":
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lasmim_fb0, lasmim_fb1, lasmim_dvi0, lasmim_dvi1 = (self.lasmixbar.get_master() for i in range(4))
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if platform_name == "m1":
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lasmim_fb = self.lasmixbar.get_master()
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if with_memtest:
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lasmim_mtw, lasmim_mtr = self.lasmixbar.get_master(), self.lasmixbar.get_master()
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req_queue_size=8,
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read_time=32,
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write_time=16
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)
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
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nphases=2, cl=3, rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
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self.create_sdram_modules(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
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#
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# WISHBONE
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#
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self.submodules.cpu = lm32.LM32()
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# Wishbone
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self.submodules.norflash = norflash.NorFlash(platform.request("norflash"), 12)
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self.submodules.sram = wishbone.SRAM(sram_size)
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self.submodules.minimac = minimac3.MiniMAC(platform.request("eth"))
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, lasmim_wb)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR()
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self.add_wb_slave(lambda a: a[26:29] == 0, self.norflash.bus)
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self.add_wb_slave(lambda a: a[26:29] == 3, self.minimac.membus)
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# norflash 0x00000000 (shadow @0x80000000)
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# SRAM/debug 0x10000000 (shadow @0x90000000)
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# USB 0x20000000 (shadow @0xa0000000)
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# Ethernet 0x30000000 (shadow @0xb0000000)
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# SDRAM 0x40000000 (shadow @0xc0000000)
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# CSR bridge 0x60000000 (shadow @0xe0000000)
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self.submodules.wishbonecon = wishbone.InterconnectShared(
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[
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self.cpu.ibus,
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self.cpu.dbus
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], [
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(lambda a: a[26:29] == 0, self.norflash.bus),
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(lambda a: a[26:29] == 1, self.sram.bus),
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(lambda a: a[26:29] == 3, self.minimac.membus),
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(lambda a: a[27:29] == 2, self.wishbone2lasmi.wishbone),
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(lambda a: a[27:29] == 3, self.wishbone2csr.wishbone)
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],
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register=True)
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#
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# CSR
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#
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self.submodules.crg = mxcrg.MXCRG(MXClockPads(platform), clk_freq)
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self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
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self.submodules.identifier = identifier.Identifier(self.known_platform_id[platform_name], int(clk_freq),
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log2_int(l2_size))
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self.submodules.timer0 = timer.Timer()
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if platform_name == "mixxeo":
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self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
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if platform.name == "mixxeo":
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
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self.submodules.fb = framebuffer.MixFramebuffer(platform.request("vga_out"), platform.request("dvi_out"),
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lasmim_fb0, lasmim_fb1)
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self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), lasmim_dvi0)
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self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), lasmim_dvi1)
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if platform_name == "m1":
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if platform.name == "m1":
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self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
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self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
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self.submodules.fb = framebuffer.Framebuffer(platform.request("vga"), None, lasmim_fb)
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if with_memtest:
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self.submodules.memtest_w = memtest.MemtestWriter(lasmim_mtw)
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self.submodules.memtest_r = memtest.MemtestReader(lasmim_mtr)
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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#
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# Interrupts
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#
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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if hasattr(self, k):
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self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
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#
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# Clocking
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#
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# Clock glue
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
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]
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def _get_vga_dvi(platform):
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try:
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pads_vga = platform.request("vga_out")
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except ConstraintError:
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pads_vga = None
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try:
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pads_dvi = platform.request("dvi_out")
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except ConstraintError:
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pads_dvi = None
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return pads_vga, pads_dvi
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class FramebufferSoC(MiniSoC):
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def __init__(self, platform, with_memtest):
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MiniSoC.__init__(self, platform, with_memtest)
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pads_vga, pads_dvi = _get_vga_dvi(platform)
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self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi, self.lasmixbar.get_master())
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class VideomixerSoC(MiniSoC):
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def __init__(self, platform, with_memtest):
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MiniSoC.__init__(self, platform, with_memtest)
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pads_vga, pads_dvi = _get_vga_dvi(platform)
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self.submodules.fb = framebuffer.MixFramebuffer(pads_vga, pads_dvi,
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self.lasmixbar.get_master(), self.lasmixbar.get_master())
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self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), self.lasmixbar.get_master())
|
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self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1), self.lasmixbar.get_master())
|
||||
|
||||
SoC = VideomixerSoC
|
||||
|
|
Loading…
Reference in New Issue