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fhdl/specials/Memory: automatic name#

This commit is contained in:
Sebastien Bourdeauducq 2013-03-12 15:58:39 +01:00
parent 04df076fba
commit 4ada2ead05
1 changed files with 3 additions and 3 deletions
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6
migen/fhdl/specials.py
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@ -1,6 +1,6 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
from migen.fhdl.tools import list_signals, value_bits_sign from migen.fhdl.tools import list_signals, value_bits_sign
from migen.fhdl.tracer import get_obj_var_name
from migen.fhdl.verilog import _printexpr as verilog_printexpr from migen.fhdl.verilog import _printexpr as verilog_printexpr
class Special(HUID): class Special(HUID):
@ -180,13 +180,13 @@ class _MemoryPort:
self.clock_domain = clock_domain self.clock_domain = clock_domain
class Memory(Special): class Memory(Special):
def __init__(self, width, depth, init=None, name="mem"): def __init__(self, width, depth, init=None, name=None):
Special.__init__(self) Special.__init__(self)
self.width = width self.width = width
self.depth = depth self.depth = depth
self.ports = [] self.ports = []
self.init = init self.init = init
self.name_override = name self.name_override = get_obj_var_name(name, "mem")
def get_port(self, write_capable=False, async_read=False, def get_port(self, write_capable=False, async_read=False,
has_re=False, we_granularity=0, mode=WRITE_FIRST, has_re=False, we_granularity=0, mode=WRITE_FIRST,