build/osfpga: Fix and switch to Raptor toolchain/Gemini device.
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parent
19d20786e3
commit
4b320a6a45
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@ -22,6 +22,7 @@ class OSFPGAToolchain(GenericToolchain):
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attr_translate = {}
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attr_translate = {}
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def __init__(self, toolchain):
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def __init__(self, toolchain):
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super().__init__()
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self.toolchain = toolchain
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self.toolchain = toolchain
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self.clocks = dict()
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self.clocks = dict()
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@ -36,7 +37,7 @@ class OSFPGAToolchain(GenericToolchain):
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sdc = []
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sdc = []
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for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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sdc.append(f"create_clock -name {vns.get_name(clk)} -period {str(period)} [get_ports {{{vns.get_name(clk)}}}]")
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sdc.append(f"create_clock -name {vns.get_name(clk)} -period {str(period)} [get_ports {{{vns.get_name(clk)}}}]")
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with open(f"{build_name}.sdc", "w") as f:
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with open(f"{self._build_name}.sdc", "w") as f:
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f.write("\n".join(sdc))
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f.write("\n".join(sdc))
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return (self._build_name + ".sdc", "SDC")
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return (self._build_name + ".sdc", "SDC")
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@ -53,7 +54,7 @@ class OSFPGAToolchain(GenericToolchain):
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# Add Include Path.
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# Add Include Path.
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tcl.append("add_include_path ./")
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tcl.append("add_include_path ./")
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for include_path in platform.verilog_include_paths:
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for include_path in self.platform.verilog_include_paths:
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tcl.append(f"add_include_path {include_path}")
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tcl.append(f"add_include_path {include_path}")
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# Add Sources.
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# Add Sources.
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@ -22,7 +22,7 @@ _io = [
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class Platform(OSFPGAPlatform):
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class Platform(OSFPGAPlatform):
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def __init__(self):
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def __init__(self):
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OSFPGAPlatform.__init__(self, device="test", toolchain="raptor", io=_io)
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OSFPGAPlatform.__init__(self, device="gemini", toolchain="raptor", io=_io)
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# Minimal Design -----------------------------------------------------------------------------------
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# Minimal Design -----------------------------------------------------------------------------------
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@ -29,7 +29,7 @@ _io = [
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]
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]
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class Platform(OSFPGAPlatform):
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class Platform(OSFPGAPlatform):
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def __init__(self, toolchain="foedag", device="mpw1"):
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def __init__(self, toolchain="raptor", device="gemini"):
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OSFPGAPlatform.__init__(self, device=device, toolchain=toolchain, io=_io)
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OSFPGAPlatform.__init__(self, device=device, toolchain=toolchain, io=_io)
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -49,8 +49,8 @@ def main():
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parser = LiteXSoCArgumentParser(description="LiteX Test SoC on OS-FPGA")
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parser = LiteXSoCArgumentParser(description="LiteX Test SoC on OS-FPGA")
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target_group = parser.add_argument_group(title="Target options")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--toolchain", default="foedag", help="FPGA toolchain.")
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target_group.add_argument("--toolchain", default="raptor", help="FPGA toolchain.")
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target_group.add_argument("--device", default="mpw1", help="FPGA device.")
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target_group.add_argument("--device", default="gemini", help="FPGA device.")
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builder_args(parser)
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builder_args(parser)
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soc_core_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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args = parser.parse_args()
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