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CHANGES: Update.

This commit is contained in:
Florent Kermarrec 2024-05-17 12:57:29 +02:00
parent d5f9d57c2b
commit 4b3f147fc8
1 changed files with 4 additions and 0 deletions
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@ -12,6 +12,7 @@
- litedram/frontend/avalon : Fixed and cleaned-up.
- litex_sim/video : Fixed pixel format to RGBA.
- build/xilinx/common : Fixed missing clk parameter on XilinxSDRTristateImpl.
- soc/interconnect : Fixed CSR/LiteXModule issue on WishboneSRAM/AXILiteSRAM.
[> Added
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@ -38,6 +39,9 @@
- cores/hyperbus : Added latency configuration and variable latency support.
- cpu/cv32e41p : Added ISR support.
- litesdcard : Improved SDPHYClocker (Timings).
- cpu/vexriscv_smp : Added baremetal IRQ support.
- cpu/naxriscv : Added baremetal IRQ support.
- cpu/zynqmp : Added Ethernet, UART, I2C support and improved AXI Master.
[> Changed
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