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cores/spi_flash: On Ultrascale: CS/DI/DO also need to be access through STARTUPE3, untested yet.

This commit is contained in:
Florent Kermarrec 2023-01-25 12:19:10 +01:00
parent cc91f2ee3a
commit 4b4fc7c6c0
1 changed files with 46 additions and 32 deletions
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48
litex/soc/cores/spi_flash.py
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@ -6,14 +6,16 @@
from migen import * from migen import *
from litex.gen import LiteXModule
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.soc.cores.spi import SPIMaster from litex.soc.cores.spi import SPIMaster
# Xilinx 7-Series FPGAs SPI Flash (non-memory-mapped) ---------------------------------------------- # Xilinx 7-Series FPGAs SPI Flash (non-memory-mapped) ----------------------------------------------
class S7SPIFlash(Module, AutoCSR): class S7SPIFlash(LiteXModule):
def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6): def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq) self.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
self.specials += Instance("STARTUPE2", self.specials += Instance("STARTUPE2",
i_CLK = 0, i_CLK = 0,
i_GSR = 0, i_GSR = 0,
@ -23,7 +25,7 @@ class S7SPIFlash(Module, AutoCSR):
i_USRCCLKO = spi.pads.clk, i_USRCCLKO = spi.pads.clk,
i_USRCCLKTS = 0, i_USRCCLKTS = 0,
i_USRDONEO = 1, i_USRDONEO = 1,
i_USRDONETS = 1 i_USRDONETS = 1,
) )
if hasattr(pads, "vpp"): if hasattr(pads, "vpp"):
pads.vpp.reset = 1 pads.vpp.reset = 1
@ -38,9 +40,26 @@ class S7SPIFlash(Module, AutoCSR):
# Xilinx Ultrascale FPGAs SPI Flash (non-memory-mapped) -------------------------------------------- # Xilinx Ultrascale FPGAs SPI Flash (non-memory-mapped) --------------------------------------------
class USSPIFlash(Module, AutoCSR): class USSPIFlash(LiteXModule):
def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6): def __init__(self, sys_clk_freq, spi_clk_freq=25e6):
self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq) self.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
spi_dts = Signal(4)
spi_do = Signal(4)
spi_di = Signal(4)
self.comb += [
# D0: MOSI (Output).
spi_dts[0].eq(0),
spi_do[0].eq(spi.pads.mosi),
# D1: MISO (Input).
spi_dts[1].eq(1),
spi.pads.miso.eq(spi_di[1]),
# D2: Vpp (Output).
spi_dts[2].eq(0),
spi_do[2].eq(1),
# D3: Hold (Input).
spi_dts[3].eq(0),
spi_do[3].eq(1),
]
self.specials += Instance("STARTUPE3", self.specials += Instance("STARTUPE3",
i_GSR = 0, i_GSR = 0,
i_GTS = 0, i_GTS = 0,
@ -49,18 +68,13 @@ class USSPIFlash(Module, AutoCSR):
i_USRCCLKO = spi.pads.clk, i_USRCCLKO = spi.pads.clk,
i_USRCCLKTS = 0, i_USRCCLKTS = 0,
i_USRDONEO = 1, i_USRDONEO = 1,
i_USRDONETS = 1 i_USRDONETS = 1,
i_FCSBTS = 0,
i_FCSBO = spi.pads.cs_n,
i_DTS = spi_dts,
i_DO = spi_do,
o_DI = spi_di,
) )
if hasattr(pads, "vpp"):
pads.vpp.reset = 1
if hasattr(pads, "hold"):
pads.hold.reset = 1
if hasattr(pads, "cs_n"):
self.comb += pads.cs_n.eq(spi.pads.cs_n)
self.comb += [
pads.mosi.eq(spi.pads.mosi),
spi.pads.miso.eq(pads.miso)
]
# Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) ------------------------------------------------- # Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) -------------------------------------------------