MultiReg: remove idomain
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@ -121,7 +121,7 @@ class XilinxMultiRegImpl(MultiRegImpl):
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class XilinxMultiReg:
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@staticmethod
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def lower(dr):
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return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
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return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
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class XilinxISEPlatform(GenericPlatform):
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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