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cores/cpu/microwatt: Re-map csr/xics and keep the lower 128MBs for the SoC IO auto-allocation.

This commit is contained in:
Florent Kermarrec 2021-04-26 18:37:40 +02:00
parent 9a82fd1d54
commit 4c26dbe98f
2 changed files with 5 additions and 4 deletions
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7
litex/soc/cores/cpu/microwatt/core.py
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@ -39,9 +39,10 @@ class Microwatt(CPU):
@property @property
def mem_map(self): def mem_map(self):
return { return {
"csr": 0xc0000000, # Keep the lower 128MBs for SoC IOs auto-allocation.
"xicsicp": 0xc3ff0000, "csr": 0xc8000000,
"xicsics": 0xc3ff1000 "xicsicp": 0xcbff0000,
"xicsics": 0xcbff1000,
} }
# GCC Flags. # GCC Flags.

2
litex/soc/integration/soc.py
View File

@ -233,7 +233,7 @@ class SoCBusHandler(Module):
for _, search_region in search_regions.items(): for _, search_region in search_regions.items():
origin = search_region.origin origin = search_region.origin
while (origin + size) < (search_region.origin + search_region.size_pow2): while (origin + size) < (search_region.origin + search_region.size_pow2):
# Create a Candicate. # Create a Candidate.
candidate = SoCRegion(origin=origin, size=size, cached=cached) candidate = SoCRegion(origin=origin, size=size, cached=cached)
overlap = False overlap = False
# Check Candidate does not overlap with allocated existing regions. # Check Candidate does not overlap with allocated existing regions.